Abstract: A microcomputer includes a ROM storing various instruction codes including an invalidation instruction code for invalidating a content of an instruction decoder. The invalidation instruction code is read from the ROM and decoded in order to produce an invalidation control signal when a predetermined security execution condition is established. Thus, the security of data contained in the instruction decoder is improved by the ability to physically invalidate an operation of the instruction decoder by writing a predetermined value into the instruction decoder or by erasing its content.

Abstract: A method and system are provided in a software network using a network of disconnected servers for detecting which background data processing functions have stopped running in that network of disconnected servers. The network of disconnected servers is monitored to determine those that contain background data processing functions which have stopped running in servers which remain disconnected. Notification is provided as to which servers have stopped running but remain disconnected and which background data processing functions in the servers have stopped running. The system periodically sends a message to restart servers which contain background data processing functions which have stopped running and remain disconnected.

Abstract: A random number generating apparatus for an interface unit of a Carrier Sense with Multiple Access and Collision Detect (CSMA/CD) Ethernet data network. The interface unit includes a transmit backoff unit for implementing a backoff algorithm in response to a network collision signal and a random number. The apparatus comprises a dual mode random number generator and a multiplexer for switching the random number generator between modes in accordance with the serial address bits of a data packet being processed by the interface unit. The random number generator includes a 25 stage linear feedback shift register. The multiplexer has two signal inputs connected to outputs of the 18th and 22nd stages of the shift register respectively, a switch input connected to receive the serial address bits and an output connected in circuit to an input of the shift register.

Abstract: A channel subsystem provided for connection of a large number of peripheral devices has an event word handing facility whereby an event word for reporting a failure, etc., occurring in a peripheral device, to a main CPU, is generated and queued in a buffer that is accessible from the main CPU. The event word handling facility provided in the channel subsystem of the present invention includes: an inhibit word count register for storing a plurality of inhibit word counts whose values are set closer to the capacity of the buffer as the significance of their associated event words increases; a selector for selecting an inhibit word count appropriate to the event word to be generated; and a comparator for comparing the selected inhibit word count with the number of event words currently held in the buffer. Only when the number of event words held in the buffer is smaller than the selected inhibit word count, is an event word generated. Thus, an event word of higher significance can be notified without fail.

Abstract: A ring network of workstations interconnected on a single simplex ring is converted to duplex communications on the single ring by placing two transceivers in each workstation and adding a duplex conversion device between each workstation and its ring terminal box. One of the transceivers receives and retransmits signals in a clockwise direction around the ring; the other transceiver receives and retransmits signals in a counter-clockwise direction around the ring. The clockwise and counter-clockwise signals are superimposed on the ring but are isolated at the workstations by the duplex conversion device.

Abstract: An operation processing apparatus includes an operation executing unit having a first input connected to one end of a circular pipeline and a second input to which the operation result of a preceding feedback loop process is provided. The operation execution unit responds to an input of a data packet including a feedback loop process instruction for continuously executing multiplication and adding operations with respect to an operand included in the input data packet and an operand provided from the second input to provide the multiplication result to the other end of the circular pipeline.

Abstract: A data buffer monitor apparatus which monitors the space availability in WRITE buffer and the number of sectors available for transfer in the READ buffer and generates the OK TO TRANSFER signal. The data buffers monitor apparatus includes a READ buffer monitor, a WRITE buffer monitor and a transfer controller. The READ buffer monitor monitors the total number of sectors stored in the READ buffer, the number of sectors in the READ buffer available for transfer to the host and generates a READ OK TO TRANSFER signal if the sectors for a requested READ operation are store in the READ buffer. The WRITE buffer monitor monitors the total number of sectors in the WRITE buffer and generates a WRITE OK TO TRANSFER signal if the WRITE monitor determines that a requested WRITE operation can be performed.

Abstract: A vector multiprocessor comprises a plurality of scalar units for executing a scalar instruction and a vector unit for executing a vector instruction, and processes, through a single vector unit, vector instructions transmitted from the plurality of scalar units having architectures different from those of the vector unit. The vector unit comprises one or more instruction converting circuits, each corresponding to each of the one or more architectures of the plurality of scalar units different from the architecture of the vector unit, for converting vector instructions transmitted from the one or more scalar units into instruction forms executable in the vector unit, and a vector instruction executing unit for executing a vector instruction transmitted from the instruction converting circuit or from the scalar unit having the compatible architecture as the vector unit.

Abstract: A scheduling system and method, which employ a token passing scheme, for scheduling transmission of multimedia information between information warehouses (IWHs) and CO clusters (CCs) interconnected by ATM switch(es). Each CO cluster employs a CC schedule processor, which has means for receiving and means for storing requests for multimedia information, means for sorting and prioritizing the requests, means for forwarding requests to appropriate IWHs, and means for accepting or rejecting tokens offered by IWHs in response to a request. The IWH employs an IWH schedule processor which includes means for receiving and means for storing requests from CO clusters, means for selecting a request and generating a token to be sent to the CO cluster originating the request, and means for storing a list of CO cluster rejecting tokens. Requests received from multiple subscribers are stored, sorted, and prioritized at CC schedule processors, which forward the requests to appropriate IWHs.

Abstract: A method for providing communication between a plurality of nodes coupled in a ring arrangement, wherein a plurality of the nodes comprise processors each having a cache memory for storing a subset of shared data. Each of the nodes on the ring deposits data into a data slot during a given time period. The data deposited by each node may comprise an address field and a node field. To ensure data coherency between the caches, each processor on the ring includes a queue for saving a plurality of received data representative of the latest bus data transmitted on the bus. As each processor receives new data, the new data is compared against the plurality of saved data in the queue to determine if the address field of the new data matches the address field of any of the saved data of the queue. In the event that the new data matches one of the plurality of saved data, it is determined whether the new data represents updated data from the memory device.