Abstract: According to a high efficiency coding signal processing apparatus of the present invention, in order to suppress error propagation, effectively correct errors, and reduce a signal deterioration upon repetitive coding processing, a bit rate reduction circuit quantizes a video signal and outputs the resultant signal to low-and high-frequency encoders. A first transmission sequence packet circuit outputs low-frequency components at a predetermined period. A second transmission sequence packet circuit sequences and outputs high-frequency components. Since the low-frequency components and the high-frequency components are separately sequenced and transmitted, the low-frequency components are free from the influence of errors caused in the high-frequency components.