Abstract: The present invention provides a method for forming a CMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a substrate, a first gate positioned on the substrate being used to form a PMOS transistor of the CMOS transistor, and a second gate positioned on the substrate being used to form an NMOS transistor of the CMOS transistor. First spacers are formed on both lateral surfaces of the first gate and of the second gate. A first ion implantation process is performed to form a pair of first doped regions in the substrate, oppositely adjacent to the first gate, the pair of first doped regions to serve as heavy doped drain (HDD) of the PMOS transistor. Then the thickness of the first spacers is reduced. A second ion implantation process is performed to form a pair of second doped regions in the substrate, oppositely adjacent to the second gate, the pair of second doped regions to serve as the HDD of the NMOS transistor. Second spacers are then formed covering each first spacer.

Abstract: A process for the preparation of substrates used in the manufacture of integrated circuits wherein spin-on low dielectric constant (low-k) polymer films are applied on semiconductor substrates. A non-etchback processing of spin-on low-k polymer films, without losing the low dielectric constant feature of the film, especially in between metal lines, is achieved utilizing electron beam radiation. A polymeric dielectric film is applied and dried onto a substrate and exposed to electron beam radiation under conditions sufficient to partially cure the dielectric layer. The exposing forms a relatively more hardened topmost portion of the dielectric layer and a relatively less hardened underlying portion of the dielectric layer.

Abstract: A process for making a self-aligned select gate for a split-gate flash memory structure uses a patterned nitride layer and a photoresist layer to serve as masks to define a select gate length, facilitates a self-aligned ion implantation to form a drain region of a memory cell, and defines a distance between the select gate and the drain region.