Abstract: A transmission side generates a first frame comprising a field for storing error correction coded information and a field for storing identification information representing error correction coded information, and generates a second frame comprising a field for storing non error correction coded information, a field for storing identification information representing non error correction coded information and a field for storing an error-detecting bit. A reception side detects whether or not a received frame has an error based on bit contents of the field storing the error-detecting bit of the received frame. If the received frame has an error, a frame type is detected based on the identification information. If the detected frame type is the first type the received frame is output to a process stage. If the detected frame type is the second type the received frame is abandoned.

Abstract: In the master control unit, updated information is transferred to a slave control unit and a coherence of information between the master control unit and the slave control unit is periodically checked, thereby eliminating a difference of the internal information of the two units which execute a control, a status monitor, and a maintenance of a computer system in an on-line manner and guaranteeing the coherence. When the master control unit recognizes a difference between the information for a predetermined time or more, the slave control unit is halted and the information of the master control unit is made effective. With respect to an abnormality of the master control unit, the master control unit halts by itself. In this instance, the slave control unit is shifted to the master status and takes over the process.

Abstract: In digital data packets comprising a first datum from which a second datum can be unequivocally computed, e.g. an error correction value, one or a plurality of additional data can be introduced by manipulating said second datum without altering the structure of the data packet. For this purpose, one or a plurality of bits of the second datum are modified in an unequivocally reversible manner, e.g. inverted, according to the additional datum which is also digital. The recuperation of the additional data is effected by comparing comparative values which are obtained by reversing all possible combinations of additional data in a received data packet to a value which is computed from the first datum of the data packet: The presence of the corresponding combination of additional data results from the consistency of the latter with one of said comparative values. Another possibility is to limit the inquiry to a fraction of the possible combination.

Abstract: The expression A-sign(A), where A is a signed binary integer represented in 2's complement form, sign (A) is equal to one when A is greater than zero, sign (A) is equal to zero when A is zero, and sign (A) is equal to negative one when A is less than zero, is calculated by bit-complementingA, bit-complementing (A-1) when A is less than zero, bit-complementing A when A is equal to zero, and bit-complementing (A+1) when A is greater than zero. Zero detect for A is provided by determining whether a first carry-out bit from (A+0) and a second carry-out bit from (A+1) have different logical values. In this manner, A-sign (A) can be calculated by a general purpose computer in a single instruction cycle.

Abstract: The expression 2A+sign(A), where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero, is calculated by bit-complementing A, bit-complementing (A+A+2) when A is less than zero, bit-complementing (A+A+1) when A is equal to zero, and bit-complementing all bits except a least significant bit of (A+A+1) when A is greater than zero. Zero detect for A is provided by determining whether a first carry-out bit from (A+A+1) and a second carry-out bit from (A+A+2) have different logical values. In this manner, 2A+sign(A) can be calculated by a general purpose computer in a single instruction cycle.

Abstract: An initial estimate of a reciprocal of a square root of a floating point number is generated by subtracting the input floating point number from a constant and shifting the results to the right by one bit. Additionally, the initial estimate of a reciprocal of a square root of a floating point number can be determined by decrementing the exponent by one, shifting the exponent and fraction to the right by one bit, and subtracting the result from predetermined constant. The estimate for the reciprocal square root can also be determined by shifting the floating point number to the right by one bit and subtracting the shift result from a predetermined number to generate the initial estimate.

Abstract: Digital filter bank device that operates in a frequency-time hierarchically arranged, recursively fed back scheme based on the concept of decimation of a multi-speed-rate-operated system. The digital filter bank device operates in accordance with the computational requirement of summation of products for generating a filter output signal, and the computations are performed according to a software scheme based on a distributed arithmetic algorithm. The use of minimum hardware is enabled by a time-multiplexed scheme for both the implementation of the decimation and the distributed arithmetic principles of signal processing. The use of such a digital filter bank device results in a digital filter hardware architecture that has a significantly reduced semiconductor device die surface area.

Abstract: A process for operating a permeable membrane generator at above or below design conditions therefor, which entails adjusting the permeation temperature of a feed stream permeating said membrane generator by heating or cooling means, thereby providing a desired amount, purity and pressure of a product gas.

Abstract: An error sensing method for increasing error control accuracy and efficiency of a data block having a plurality of ECC (error control code) coded words transmitted through a communication media, the method comprising the steps of:(1) inserting a plurality of sensing bits into one or more predetermined positions within the data block;(2) modulating and transmitting the data block to the communication media;(3) receiving and demodulating the data block from the communication media;(4) extracting the sensing bits out of the received data block and calculating a BER by using the extracted sensing bits; and(5) requesting for retransmission if the BER of the received data block is worse than a predetermined BER1 which is approximately equal to the ratio of the number of maximum detectable errors of the ECC to the number of bits contained in one ECC coded word.

Abstract: A selected one of the expressions 2A+sign(A), 2A-sign(A), A+sign(A), and A-sign(A) is calculated, where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero. Advantageously, the selected sign 3 expression can be calculated by a general purpose computer in a single instruction cycle.

Abstract: Accessory for a laptop computer with LCD display which is connected to the laptop serial communications port and optically transmits data to a portable information device, such as a wristwatch designed to receive data as sequential pulses of light. The accessory includes a microcomputer with an RC timebase which is calibrated each time it is used by a special internal program, so that the input baud rate to the accessory matches the communications baud rate of the data received from the laptop. The internal program also permits selection of an output baud rate for the optically transmitted data.

Abstract: In order to transmit information data from a station to another station through a transmission channel, only the information data (a.sub.31 to a.sub.00, b.sub.31 to b.sub.00, etc) are transmitted when the channel has a good channel quality. When the channel quality is bad, error correction code words are composed for transmission by adding redundancy bits (A.sub.15 to A.sub.00, B.sub.15 to B.sub.00, etc) to the information data. When the channel quality is bad even with transmission of the code words, error correction code blocks are composed by interleaving information bits (a's, b's, etc) and the redundancy bits in a selected number of code words with the selected number increased from two depending on the channel quality. Alternatively, such data, words, or blocks are transmitted with a transmission rate adjusted.

Abstract: A leading zero anticipatory logic circuit generates a first result by AND operation of ith bit (i is an integer; 1.ltoreq.i.ltoreq.m) of a first mantissa and an ith bit of a second mantissa; generates a second result by NOR operation of the ith bit of the first mantissa and the ith bit of the second mantissa; generates a third results by an OR operation of the first and second results; generates a fourth result by OR operation of the (i-1)th bit of the first mantissa and the (i-1)th bit of the second mantissa; and generates a leading-zero anticipatory bit E.sub.i of the ith digit by an AND operation of the third and fourth results. Based on the counted number of the leading-zero anticipated by leading-zero anticipatory logic circuit, shifter circuits shift the result of addition.

Abstract: The expression A+sign(A), where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero, is calculated by bit-complementingA, bit-complementing(A+1) when A is less than zero, bit-complementing A when A is equal to zero, bit-complementing(A-1) when A is greater than zero and odd, and bit-complementingall bits except a least significant bit of A when A is greater than zero and even. Zero detect for A is provided by determining whether a first carry-out bit from (A+0) and a second carry-out bit from (A+1) have different logical values. In this manner, A+sign(A) can be calculated by a general purpose computer in a single instruction cycle.

Abstract: The expression 2A-sign(A), where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero, is calculated by bit-complementing A, bit-complementing (A+A) when A is less than zero, bit-complementing (A+A+1) when A is equal to zero, and bit-complementing (A+A+2) when A is greater than zero. Zero detect for A is provided by determining whether a first carry-out bit from (A+A+1) and a second carry-out bit from (A+A+2) have different logical values. In this manner, 2A-sign(A) can be calculated by a general purpose computer in a single instruction cycle.

Abstract: The invention is a way to detect and correct data inversions or other phase ambiguities in a modem's data, without incurring a significant penalty in error rate performance, throughput, or overhead, by making a particular use of the error detection and correction (EDAC) code which would typically be used for random errors. The decoder is set up so that the inverted data or out-of-phase data generates a distinctive syndrome which signals to a phase corrector.

Abstract: A marking apparatus with a CAD device which is highly productive due to the procedure of entering an image of a workpiece 1 as a marking diagram into the CAD device 40 and constructing a work program synthesizing the marking symbols/drawings onto the marking diagram. The position of the workpiece 1 can be adjusted by monitoring the screen because an image of the workpiece 1 is displayed on the display device 4N of the CAD device 40 as a marking diagram. Additionally, marking symbols/drawings of an arbitrary scale can be synthesized in cooperation with the marking diagram of the workpiece, since the scaling ratio of the image of the workpiece 1 is displayed on the display device 4N.

Abstract: A method is described for detecting the time messages in the faulty signal of a time-signal transmitter comprising the steps below. Probabilities are assigned to the received information/bits as they are received and whose sign specifies the value of the bit and whose numerical value indicates the certainty of reception. Except for the bits designating the minute information, the probabilities of successive time messages are totaled with time correctness in a one-dimensional memory field. From the totaled probabilities, a reduced time message is reconstructed that initially contains no information on the minutes. If the reconstructed time message does not change over two successive time intervals, and if preset minimum values for the number of probabilities are exceeded for all bits, then the reduced time message is recognized as being correct. The minutes are determined separately and added to the time message recognized as being correct.

Abstract: Improved and less complicated leading bit anticipation (LBA) for a PKG floating point adder of n-bit 2's complement operands is accomplished by representing de-normalized (n+1)-bit operands as (n+1)-many PKG symbols. These are grouped into (n-1)-many triples, each of which has two adjacent PKG symbols in common with its neighboring triple. Presuming the existence of a least significant PKG symbol of K allows the formation of an additional triple of lesser significance. Each triple produces an associated transition bit that when set indicates, for the partial summation segment of the raw sum of bit location corresponding to the location of the triple, if the left-most two bits of the corresponding partial summation segment are, or would be with a carry-in, of opposite bit values. The bit position of the most-significant set transition bit is determined in terms of how many bit positions J that is from the most significant transition bit position.

Abstract: Zero detect of a sum of binary operands is disclosed. If the sum is zero, the bit-complement of the sum is a string of one's, and therefore incrementing the string of one's generates a carry-out bit of one. Likewise, if the sum is non-zero, the bit-complement of the sum will contain one or more zero's, and therefore incrementing the bit-complemented sum will not generate a carry-out bit of one. One embodiment includes providing a result representing a bit-complement of the sum, and then inspecting a carry-out bit generated by incrementing the result. Another embodiment includes bit-complementing first and second operands, generating a first carry-out bit from a sum of the bit-complemented first and second operands and a constant of one, generating a second carry-out bit from a sum of the bit-complemented first and second operands and a constant of two, and setting a zero detect flag to TRUE when an EXCLUSIVE-OR of the first carry-out bit and the second carry-out bit is a one.