Patents Examined by Robert Kimanek
  • Patent number: 5173752
    Abstract: A semiconductor device incloudes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.
    Type: Grant
    Filed: April 26, 1991
    Date of Patent: December 22, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kaoru Motonami, Natsuo Ajika, Atsushi Hachisuka, Yoshinori Okumura, Yasushi Matsui