Patents Examined by Robert Konemund
  • Patent number: 5563104
    Abstract: An improved method of ozone-TEOS deposition with reduced pattern sensitivity using a two-step low and high temperature process is described. Semiconductor device structures are provided in and on a semiconductor substrate. A conducting layer is deposited overlying the surfaces of the semiconductor device structures and patterned to form conducting lines. An underlayer is deposited overlying the patterned conducting layer. A dielectric layer is deposited in two steps. A first ozone-TEOS layer is deposited over the surfaces of the conducting layer at a first temperature to a first thickness. A second ozone-TEOS layer is deposited over the first ozone-TEOS layer at a second temperature and to a second thickness wherein the second temperature is higher than the first temperature and the second thickness is greater than the first thickness completing the dielectric layer.
    Type: Grant
    Filed: June 23, 1995
    Date of Patent: October 8, 1996
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Syun-Ming Jang, Lu-Min Liu