Abstract: Multiple quantum wells within an impact avalanche transit time device (IMPATT) utilizing a plurality of gallium arsenide/aluminum gallium arsenide heterojunctions are used to provide a high power, high frequency, high efficiency device operating at 50 GHz and up. The multiple quantum wells defined by the heterojunctions between pairs of gallium arsenide quantum wells and aluminum gallium arsenide barrier layers improves the nonlinearity of the avalanche process within the gallium arsenide quantum wells and reduces the ionization rate saturation limitations. Optical injection locking of the current through the IMPATT device is achieved by irradiating the active layer of the IMPATT device with modulated laser light.

Abstract: A laser is used in a non-destructive manner to detect surface and near-subsurface defects in dense ceramics and particularly in ceramic bodies with complex shapes such as ceramic bearings, turbine blades, races, and the like. The laser's wavelength is selected based upon the composition of the ceramic sample and the laser can be directed on the sample while the sample is static or in dynamic rotate or translate motion. Light is scattered off surface and subsurface defects using a preselected polarization. The change in polarization angle is used to select the depth and characteristics of surface/subsurface defects. The scattered light is detected by an optical train consisting of a charge coupled device (CCD), or vidicon, television camera which, in turn, is coupled to a video monitor and a computer for digitizing the image. An analyzing polarizer in the optical train allows scattered light at a given polarization angle to be observed for enhancing sensitivity to either surface or near-subsurface defects.

Abstract: An improved device for determining the three-dimensional location and orientation of a subject in a virtual reality simulation is a hybrid of an optical localization system and independent tilt and direction sensors. Three or more modulated sources of light or near-infrared radiation are placed at the perimeter of the sensing volume; these sources are typically emitters surrounded by rotating cylindrical grating. A single photosensor extracts enough information from the radiation field to derive position within the volume. Orientation is sensed by small gravitational tilt and magnetic compass direction sensors. Since the sensing is entirely passive, any number of objects can be tracked within the volume as long as at least three of the sources are visible from the position of each object.

Abstract: In a semiconductor device, a first gate electrode and isolation layers are formed on a first gate insulation layer on a p-type silicon semiconductor substrate, and a second gate electrode is formed on the first gate electrode with a second gate insulation layer interposed therebetween. The first gate electrode is constituted by a first polycrystalline silicon layer, a second polycrystalline silicon layer and an etching stopper thin film interposed therebetween. The first gate electrode is formed by anisotropic-etching or selectively etching the second polycrystalline silicon layer, so that the etching stopper is maintained.

Abstract: A semiconductor device capable of improving pressure-resistant and leakage-resistant characteristics of a stacked type capacitor formed on a planarized insulating layer. The semiconductor device includes a plug electrode layer 313 of at least one material selected from the group consisting of TiN, Ti, W, and WN, buried in a contact hole 311a of an interlayer insulating films 311 and extending on and along the upper surface of interlayer insulating film 311. As a result, creation of a stepped portion on platinum layer 314 constituting a capacitor lower electrode to be formed on the plug electrode 313 is prevented, and the thickness of a PZT film 315 to be formed on platinum layer 314 is not disadvantageously made thin at the stepped portion.

Abstract: A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three factors in increasing the effective area for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterened to selectively remove the storage poly layer, and the spacer maximizes the size of the storage poly; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a plat poly material is coated and wrapped.

Abstract: The present invention teaches a memory comprising an array of memory cells. Each cell of the array in the memory comprises a bus, and a diode, preferably a zener diode, having a substantially low breakdown voltage. Further, each cell comprises a programmable element, preferably an antifuse, for selectively coupling the diode with the bus.

Abstract: A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N-epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor.

Abstract: A memory cell is formed in the main surface area of a semiconductor substrate. An inter-level insulation film is formed on the substrate to cover the memory cell. An opening is formed in the inter-level insulation film to reach the memory cell. An internal wiring layer is electrically connected to the memory cell via the opening. A protection film is formed on the inter-level insulation film to cover the internal wiring layer. The protection film is formed of a material containing at least silicon and oxygen and the refractive index thereof is set within a range of 1.48 to 1.65.

Abstract: A metal-to-metal antifuse includes a lower electrode formed from a first metal layer in a semiconductor or other microcircuit structure. A barrier layer is disposed over the first metal layer. A first heavily-doped amorphous silicon layer is disposed over the barrier layer. A thin dielectric antifuse material is disposed over the first amorphous silicon layer. This dielectric can be nearly any dielectric such as nitride or oxide or a combination of these materials such as ONO and should have a breakdown voltage suitable for programming inside the integrated circuit. A second heavily-doped amorphous silicon layer is disposed over the dielectric layer. An upper electrode, comprising a second metal layer including an underlying barrier layer, is disposed over the second amorphous silicon layer. The first and second metal layers may comprise metal interconnect layers in the circuit structure.

Abstract: A vertical type surge protection device for absorbing surges of either polarity has a second region forming a first pn junction with a first region, a third region forming a first minority carrier injection junction with respect to the second region, a fourth region forming a second pn junction with the first region and a fifth region forming a second minority carrier injection junction with the fourth region. When the absolute value of a surge voltage applied across the device exceeds the breakdown voltage, either the one of the first and second pn junctions that is reverse biased owing to the surge polarity breaks down or punch-through occurs between the first and third regions or between the first and fifth regions, whereafter breakover ensues as a result of positive feedback.

Abstract: The present invention is directed to a semiconductor memory device and a method for fabricating a semiconductor memory device, in particular a E.sup.2 PROM, having an improved tunnel area wherein electrons travel to and from a floating gate. The tunnel area is characterized by properties which lend to a relatively large number of programming and erasure cycles over the life of the E.sup.2 PROM. The tunnel area includes a tunneling gate which is fabricated via two implant stages. Because these two stages are separate from one another, each of the implant stages can be independently optimized to improve the properties of the tunnel area. Further, the windows used to define the implant regions are easily fabricated and are designed to facilitate formation of the implant regions. The method of defining the window lends to easy scaling of the process for advancing generations of technology.

Abstract: In a storage device, such as a magnetic rigid disk drive, data is stored at varying linear densities in the user data storage portions to increase the effective storage capacity of the device as a function of the differences in soft error rate tolerance associated with the various types of data being stored and the ability of non-alphanumeric data to be enhanced by reconstruction or smoothing rather than by an error correction code. A data type signal included with incoming data dictates the recording frequency and a control signal associated with the recorded data block is read when data is addressed to appropriately adjust the clock frequency for reading such addressed stored data.

Abstract: In a memory construction using ferroelectric film, by embedding a capacitor formed by said ferroelectric film in a through hole bored in an interlayer insulating film formed on a semiconductor substrate, reliability of the wiring layer passing thereover so as to obtain a highly reliable semiconductor memory by reducing the step difference by said capacitor.

Abstract: A compound semiconductor device including a semiconductor substrate having (100) plane as a crystal growth plane, a first semiconductor layer as an electron traveling layer and a second semiconductor layer for supplying electrons to the electron traveling layer. The first semiconductor layer is formed on the semiconductor substrate and has a different lattice constant from the semiconductor substrate so that a first strain is applied in the first semiconductor layer in a first strain direction. The second semiconductor layer is formed on the first semiconductor layer and has a different lattice constant from the first semiconductor layer to thereby apply a second strain to the second semiconductor layer. The second strain has a direction that is inverse to the first strain direction. In addition, the thickness of the semiconductor layer is defined so as to compensate for the first strain applied to the first semiconductor layer by the second strain applied to the second semiconductor.

Abstract: A non-volatile semiconductor memory including a semiconductor substrate, drain and source regions which are provided on the surface of the semiconductor substrate and have P or N type differently from the semiconductor substrate, a floating gate (first gate electrode) for covering a portion of a channel region between the drain and source regions, the drain region being self-aligned with the floating gate, the source region being provided apart from the floating gate through an offset region in the channel region by a constant distance, whereby the drain and source regions are asymmetrical to each other through the floating gate, a control gate (second gate electrode) for controlling the surface potential of the whole channel region, and a third gate electrode provided above the control gate through an insulating film for substantially controlling the surface potential on the underside of the floating gate and in the vicinity thereof so that electrical writing and erasure can be performed, wherein the density

Abstract: The input/output circuit cells of a master-slice gate array device have the same diffusion and gate regions as the basic transistors so that the input/output of the device may be defined at the metallization stage rather than at the time the diffusion regions are formed. Thus a single size master-slice circuit device need to be kept in inventory. The array size is selected in accordance with the customer's specification and the inputs/outputs are defined accordingly using CAD. Thereafter, the die may be scribed into smaller. The transistors for sea-of-gate structures containing a pair of long channel transistors whose drain, gate and source regions lie on a single grid or track of the CAD design tool. By using a long channel transistor in the feedback loop of a memory cell, gating transistors may be eliminated to reduce transistors required for latches.

Abstract: Multiple punchthru devices are coupled between multiple metal-two conductors and a metal-one bond pad. Each punchthru device has the capacity to couple its respective metal-two conductor to the bond pad when a predetermined voltage potential exists between the metal-two conductor and the bond pad. A set of metal-one islands, one set associated with each metal-one bond pad cell, resides in a bond pad channel. The positioning of the punchthru devices and the islands minimizing the bond pad cell size and minimizing the spacing between adjacent bond pad cells. The bond pad cell configuration also allows any metal-two conductor to be coupled to the bond pad without having to rearrange punchthru devices or reconfigure the bond pad cell. The multiple punchthru devices associated with each bond pad cell provide redundant overvoltage protection superior to present overvoltage protection circuits.

Abstract: A non-mechanical beam deflector forms and scans a beam of millimeter wave (MMW) radiation at a rapid rate. The beam deflector includes a semiconductor body in which a spatially varying density of charge carriers is selectively injected. The injected charge carriers--electrons and/or holes--alter the dielectric constant of the semiconductor body locally and thereby attenuate and reflect incident MMW radiation. The portions of the semiconductor body that do not have carriers injected therein allow the incident MMW radiation to be transmitted. The semiconductor body, modified with a spatially varying density of charge carriers, diffracts the radiation which passes through it into a beam. The beam may be scanned across space through selective control of the injected charge carriers. The diffractive conditions can be rapidly re-configured.

Abstract: A semiconductor memory device comprising a semiconductor substrate, a MOS transistor formed on the semiconductor substrate and having source and drain diffused layers and a gate, an interlayer insulating film covering the MOS transistor, a contact hole formed in the interlayer insulating film so as to reach one of the source and the drain diffused layers, a metallic layer filling up the contact hole and a capacitor formed on the interlayer insulating film and connected electrically to the one diffused layer through the metallic layer.