Abstract: Resets on a data processing system are targeted to specific locations of that processing system and have different effects. Some resets are transparent to instruction execution while other resets will interrupt the normal execution of instructions. In addition, in a multi-zone environment resets in one zone do not automatically propagate to the other zone; instead, each zone generates its own resets.

Abstract: A method and apparatus for non-sequential access to shared resources in a multiple requestor system uses a variety of tags to effectively re-order the data at its destination. In simplest form, the tag directs switching logic to where in a buffer to locate another tag for direction information or where in a buffer or processor (register) to put the response associated with the tag. For example, loading data from memory requires that the requestor provide a request signal, an address, and a request tag. The request signal validates the address and request tag. The address specifies the location of the requested data in memory. The request tag specifies where to put the data when it is returned to the processor.

Abstract: A data processing system for allocating a plurality of peripheral storages to a plurality of users comprises a data processing device, a plurality of peripheral storages connected with the data processing device, a catalog control unit for setting on a table a total usage capacity of the usable space set by users including an active pool having a plurality of peripheral storages to which files are allocated and an inactive pool for holding files which are migrated from the active pool, a file allocating unit which sets the current usage capacity on a table depending upon the use of space of said active pool to compare the sum of the added space capacity inputted by users and the current usage capacity with said total usage capacity for deciding an error of allocation of the added peripheral storage when the sum is larger than the latter.

Abstract: A network station's elasticity buffer includes a memory core together with write and read pointer logic. The memory core includes a START area and a CONTINUATION area which is a cyclic buffer. Under normal conditions, the read pointer follows the write pointer cyclically in the CONTINUATION area. However, upon detection of a start delimiter or upon station reset, the pointers recenter to the START area. Separate synchronizing logic is provided for each of the two recentering modes to reduce metastability problems caused by asynchronous sampling of data.

Abstract: A symbol-wide elasticity buffer for a receive/transmit station within an asynchronous data transmission network provides both for reframing after each packet and for the handling of a continuous line state symbol for a period longer than the allowed packet size. According to one aspect of the invention, the elasticity buffer is divided into a START section and a CONTINUATION section. The buffer's write pointer will not enter the CONTINUATION section until the read pointer is directed to the first of the multiple, sequential registers comprising the START section. The read pointer must sequentially read the START section registers before entering the CONTINUATION section. Once the write pointer or read pointer leaves the START section, it can only reenter the START section upon receipt of a start delimiter signal. When the write pointer or the read pointer reaches the last register in the CONTINUATION section, it is automatically routed back to the first CONTINUATION section register.

Abstract: Apparatus for assigning addresses to devices connected to a small computer system interface (SCSI) bus. A second configure bus interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

Abstract: In a microprocessor system provided with a central processing unit with an internal address and data bus arrangement connected to the central processing unit and to an operation codes memory (ROM) the clock of an external serial bus is obtained from connection to the least significant bit wire of the internal address bus. The central processing unit is operated in such a way that the addresses carried by the address bus, during an operation of writing on the external serial bus, are regularly incremented by unity, producing in the least significant bit wire a sequence of alternating ONES and ZEROS. For this purpose, the operation codes memory contains, in the locations corresponding to the addresses present on the internal address bus during a write operation, operation codes intended to establish the value of the datum on a port of the central processing unit to which the data wire of the external serial bus is connected.

Abstract: An apparatus for use with a computing device for controlling communications with a plurality of peripheral devices, each of which peripheral devices is operatively connected with a bus and is identified by an address. The apparatus comprises a control circuit for transmitting address information to the bus to effect interrogation of the plurality of peripheral devices, respective of the pluraity of peripheral devices being responding, or ready, peripheral devices according to address information transmitted by the control circuit. A plurality of modal circuits are provided for establishing a plurality of operational modes for the apparatus, as well as a decision circuit for effecting designation of selected of the plurality of modal circuits.

Abstract: A transparent system interrupt is invoked by the assertion of an electrical signal at an external pin of a microprocessor CPU chip. Upon assertion of this interrupt, the CPU begins program execution in a dedicated RAM area that is inaccessible both to the operating system and all application programs. A set of instructions, which may be unique to the system in which the CPU chip is installed, services the interrupt. Typically, the state of the CPU and associated components in the system immediately prior to assertion of the interrupt will be saved into the dedicated RAM area by the interrupt service routine. Recovery from the interrupt is accomplished upon recognition of an external event that invokes a RESUME instruction causing the CPU and associated components to be restored to exactly the same state that existed prior to the interrupt and in a manner entirely transparent to any program executing at the time of the interrupt.

Abstract: An ARINC Specification 429 transmitter provided with self test capability. A dual transmitter (10) converts parallel data provided from an external source through a bidirectional data bus (12) to a serial data format corresponding to Aeronautical Radio Incorporated (ARINC) Specification 429. The dual transmitter includes two first-in-first-out (FIFO) storage buffers (20a, 20b), which may be used separately by each transmitter, or alternatively may be daisy chained to provide 128 words of buffered storage for one of the transmitters. One of two different fault detection tests or modes is enabled upon hardware or software reset of the dual transmitter. In a scan test mode, the dual transmitter transmits ARINC data while generating a signature value corresponding to the data for comparison to an expected signature value generated by an external microporcessor or computer, to detect errors in the data input to the device or a fault in the internal circuitry of the dual transmitter.

Abstract: An apparatus for managing transfer of a packet of information to one of a plurality of ports with each the port having an associated port speed includes a double linked list transmit queue and a plurality of port queues corresponding to the plurality of ports. The packet is read to determine a priority and destination port of the packet. A loadsheding value correlating to the packet's destination port and priority is determined and compared with a measure of the amount of free space in the transmit queue. The packet is loaded into the transmit queue if the loadsheding value is less than or equal to the measure of the amount of free space in the transmit queue. The packet is discarded in the event the loadsheding value is greater than the measure of the amount of free space in the transmit queue.

Abstract: Microcontroller comprising in particular a central processing unit (10), a set of memories (11, 12), a specialized processing module (13) for performing, in sequence, operations on v variable operands and k operands of parameter type (constant during the sequence), and an arrangement of internal buses (20, 21) for the exchange of addresses and data.

Abstract: A single-chip microcomputer has a clock-signal generating circuit which includes a main system-clock oscillation circuit for generating a main clock-signal, a sub system-clock oscillation circuit for generating a sub clock-signal, a selector flag setter for setting a selector flag, an oscillation control flag setter for setting an oscillation control flag, and a synchronization control circuit for effecting synchronization between the main clock-signal and the sub clock-signal. The clock-signal generating circuit of the invention has a logic circuit which takes a logical AND operation of outputs of the oscillation control flag setter, the selector flag setter and the synchronization control circuit and which outputs an oscillation control signal for stopping oscillating operation of the main system-clock oscillation circuit.

Abstract: A personal computer system is provided with a detachable hard disk pack, a lock mechanism for locking the hard disk pack into the system, a switch which turns on and off in cooperation with the lock and release operations of the lock mechanism. When the hard disk pack is detached from the system, while the system is being powered, the switch turns off in cooperation with the release operation of the lock mechanism. In response to the changed state of the switch, the NMI control section outputs an NMI signal to the CPU. In response to the NMI signal, the CPU instructs a power controller to cut off the power. The CPU determines in response to the system being powered if the hard disk pack is attached to the system. If the hard disk pack is not attached, the CPU instructs the power controller not to supply the power to the system.

Abstract: A link-level facility for managing the transmission of frames and continuous sequences of control characters over a link. The link-level facility includes a state machine which has a first state for allowing transmission of a frame over the link where a link-level facility at the other end of the link indicates that the link has a frame-transmitting status, and a second state for preventing the transmission of frames over the link when the link-level facility at the other end of the link has indicated that the link has a non-frame-transmitting status. The link-level facilitates signal the status of the link by means of continuous sequences of special characters intermediate frames transmitted over the link such that synchronism is maintained. The first state includes an inactive state and a working state, and the second state includes a link-failure state, and connection-recovery state and an off-line state.

Abstract: A data processing device includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Abstract: A monitor control system comprises an interrupt processor for executing regular monitor processing by a periodic interrupt occurring at a predetermined time interval, and a background processor for executing background processing, wherein when interruption occurs, execution of the background processing by the background processor is interrupted while regular monitor processing is executed during a period in which background processing is interrupted. The time-consuming background processing is treated as a low-level processing task, and the regular monitor processing, as a high-level processing task. The low-level processing task is executed as a background processing during CPU idle time. Interruption of the background processing occurs ever 10-msec, during which the high-level processing task is executed. Accordingly, background processing and regular monitor processing are smoothly executed, and the CPU is thereby efficiently used.

Abstract: An information processing system includes a processor, a main storage, a buffer storage for holding a copy of a part of data of the main storage, an address translator for translating a logical address composed of a page address portion and an address portion within the page into a real address and a system controller and a buffer storage control unit. The buffer storage control unit includes a first detector and a second detector.

Abstract: An external signal processor is provided for use with a personal computer. The signal processor incorporates hardware components for receiving external analog or frequency signals and for converting the signals to digital form for retrieval by the computer in nibble mode. Interconnection with the personal computer is through the parallel printer port, with the signal processor installed between the computer and an external printer. Normal printer functions are available when a transparent mode is enabled. The signal processor can also monitor one or more external digital signals and output one or more digital control signals. An example of programmable control software is also provided.

Abstract: A semiconductor integrated-circuit card including a microprocessor having an active mode of operation capable of processing data and a low power consumption mode of operation disabled from processing data, the microprocessor being operative to (1) establish the low power consumption mode of operation in the IC card when the microprocessor is initially activated to start operation, (2) make a shift from the low power consumption mode of operation to the active mode of operation responsive to an interrupt signal from an external signal source, and (3) make a shift from the active mode of operation back to the low power consumption mode of operation upon termination of the data processing in the active mode of operation.