Patents Examined by Robert W. Doans
  • Patent number: 5305425
    Abstract: For an input value, conformity grades are computed and are displayed for established membership functions. Alternatively, conformity grades and change rates thereof developed when a fuzzy reasoning system is operated are displayed. Alternatively, a change with respect to time of the input value is displayed to be superimposed onto a table representing the established rules. Alternatively, an output value resultant from a fuzzy reasoning conducted with a particular rule removed is compared with a fuzzy reasoning achieved by using all rules, thereby displaying the difference on a rule table. As above, various features in the fuzzy reasoning are extracted and are displayed so as to check adequacy of the established membership functions and rules.
    Type: Grant
    Filed: December 30, 1991
    Date of Patent: April 19, 1994
    Assignee: Omron Corporation
    Inventors: Tsutomu Ishida, Nobuo Tsuchiya, Kazuaki Shoji, Nobutomo Matsunaga
  • Patent number: 5303329
    Abstract: A continuous weight-update device for a synaptic element including at least one MOS transistor comprises a floating node having a capacitance associated therewith, the floating gate comprising at least a part of the floating node, first and second input lines, first and second error lines, an electron tunneling structure coupled to the floating node for tunneling electrons from the floating node, and an electron injecting structure coupled to the floating node for injecting electrons onto the floating node. Control circuitry is responsive to signals on the first input and error lines, for activating the electron tunneling structure, and control circuitry is responsive to signals on the second input and error lines, for activating the electron injecting structure. Circuitry is provided for driving signals onto the first and second input and error lines. Both a single synapse and an array of synapses incorporating the continuous weight-update device are also taught.
    Type: Grant
    Filed: December 10, 1991
    Date of Patent: April 12, 1994
    Assignee: Synaptics, Incorporated
    Inventors: Carver A. Mead, Janeen D. W. Anderson, John C. Platt
  • Patent number: 5303328
    Abstract: A neural network system includes an input unit, an operation control unit, a parameter setting unit, a neural network group unit, and a display unit. The network group unit includes first and second neural networks. The first neural network operates according to the mean field approximation method to which the annealing is added, whereas the second neural network operates in accordance with the simulated annealing. Each of the first an second neural networks includes a plurality of neurons each connected via synapses to neurons so as to weighting outputs from the neurons based on synapse weights, thereby computing an output related to a total of weighted outputs from the neurons according to an output function. The parameter setting unit is responsive to a setting instruction to generate neuron parameters including synapse weights, threshold values, and output functions, which are set to the first neural network and which are selective set to the second neural network.
    Type: Grant
    Filed: October 24, 1991
    Date of Patent: April 12, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Hironari Masui, Ikuo Matsuba
  • Patent number: 5220643
    Abstract: A neural plane, which can form the basis of a neural network or a component thereof, is comprised by an optical modulator, an electrical non-linearity circuit and an optical detector interconnected whereby in use the non-linearity circuit controls the modulator in dependence on the detector output. There are parallel arrays (10, 11, 12) of such modulators, non-linearity circuits and detectors (M, T, D, 30, 33, 34). The modulator, non-linearity circuits and detectors have components formed in a common semiconductor substrate (20), for example by VLSI techniques with a silicon substrate, the modulators (30) may be comprised by liquid crystal on silicon in that case (FIGS. 4, 7).
    Type: Grant
    Filed: May 24, 1990
    Date of Patent: June 15, 1993
    Assignee: STC PLC
    Inventor: Neil Collings
  • Patent number: 5155801
    Abstract: A plurality of neural networks are coupled to an output neural network, or judge network, to form a clustered neural network. Each of the plurality of clustered networks comprises a supervised learning rule back-propagated neural network. Each of the clustered neural networks are trained to perform substantially the same mapping function before they are clustered. Following training, the clustered neural network computes its output by taking an "average" of the outputs of the individual neural networks that make up the cluster. The judge network combines the outputs of the plurality of individual neural networks to provide the output from the entire clustered network. In addition, the output of the judge network may be fed back to each of the individual neural networks and used as a training input thereto, in order to provide for continuous training. The use of the clustered network increases the speed of learning and results in better generalization.
    Type: Grant
    Filed: October 9, 1990
    Date of Patent: October 13, 1992
    Assignee: Hughes Aircraft Company
    Inventor: William P. Lincoln