Patents Examined by Rolf Hile
  • Patent number: 4977436
    Abstract: A high density DRAM having a plurality of cells each including a storage capacitor and a single control FET formed together in a trench to substantially reduce planar area of the cell. The FET drain is formed in the upper portion of a pedestal and is accessible externally through a metal line, which reduces line resistance and capacitance. Field oxide is included to isolate capacitors and reduce leakage and breakdown.
    Type: Grant
    Filed: July 25, 1988
    Date of Patent: December 11, 1990
    Assignee: Motorola, Inc.
    Inventors: Kazuhisa Tsuchiya, Yoshio Enosawa, Motohiro Kitajima