Abstract: A data demodulator for a multicode Code Division Multiple Access (CDMA) system is provided. The system transmits data by allocating multiple codes to each user. In the data modulator, a code generating part generates a local code for despreading input channel signals and local orthogonal codes for orthogonally despreading the despread channel signals. A time error estimator generates time error information for the despread channel signals and outputs the time error information to the code generating part. A symbol processing part includes N symbol processing units, where N is the number of codes allocated to each user. The N symbol processing units demodulate symbols despread by the local orthogonal codes into original symbols. A symbol deskewer classifies the demodulated symbols by the respective codes and writes the classified symbols in sequence into a two-dimensional memory.

Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Abstract: In a mobile communication system comprising a mobile station (20), a plurality of base stations (30-1 to 30-4), and an exchange station (40) connected to the base stations, a particular base station (30-1) informs, on reception of an outgoing call for the mobile station (20), the mobile station (20) of a node number for identifying the exchange station (40) and a processor number for identifying a call processing processor in the exchange station to make the mobile station (20) hold the node number and the processor number as a held node number and a held processor number. When the mobile station (20) carries out handover, the mobile station (20) sends the held node number and the held processor number to a new base station (30-2) destined for the handover. The exchange station (40) selects a call processing processor in accordance with load distribution order to make the call processing processor inherit a call processing.

Abstract: A method and apparatus for reliably detecting both AIS and AIS-CI signals in the presence of a bit error ratio up to 1×10−3 includes an AIS detector having an AIS indication output, a CI detector having a CI indication output, and a two signal AND gate having its inputs coupled to the respective outputs of the detectors and having an output indicative of an AIS-CI detection. The AIS detector has an adjustable zero threshold and the CI detector has a threshold output coupled to the AIS detector for adjusting the zero threshold. According to the method of the invention, the AIS detector zero threshold is normally set at the normal threshold (1×10−3) but is reset to a higher threshold (e.g., 2×10−3) when the CI detector detects the presence of the CI code word.

Abstract: A method of communicating between first and second controllers (including between processes within the controllers, or microprocessors) on an I2C bus is provided. The I2C bus is of the type which transmits data packets that start with a start condition and end with a stop condition, and that includes a destination address followed by a transmission type, a first data byte, a second data byte, and one or more additional data bytes. The method includes the steps of: designating a destination address with a unique bus address (i.e., devAddress) of the second controller; designating the first data byte with a unique bus address (i.e., ownAddress) of the first controller; and specifying the transmission type, wherein the first and second controllers initiate a master-slave relationship for read and write operations between controllers. The invention also provides an I2C bus protocol system. The system includes an I2C bus with means for communicating an I2C packet across the bus.

Abstract: A dynamic trunk protocol enables dynamic negotiation of trunk encapsulation types between ports connecting intermediate stations in a computer network. The stations are preferably interconnected by a point-to-point link. Negotiation between a local port and a neighbor port of the switches results in synchronization of the port configurations to a common trunk encapsulation type, such as an Interswitch Link (ISL), IEEE 802.1Q or non-trunk port configuration.

Abstract: In a general switch, a word oriented switch and a bit oriented switch are connected such that a common input signal included data appearing in time slots is provided to both switches. The general switch further includes a device for establishing, for each one of a number of outgoing time slots, at least one of a first connection path through the word oriented switch and a second connection through the bit oriented switch, and a device for selecting, for each outgoing time slot, data from an established one of the connection path. For each outgoing time slot, only one of the connection paths is established and the selecting device selects data from the established connection path.

Abstract: In a transmitter side of an image packet communications system, a transmission clock signal is generated subordinately synchronized to a reference clock signal. Based on the transmission clock signal, a transmission standard signal is generated as synchronous with the reference clock signal. Further, a packet generator generates image packets based on the timing of the transmission clock signal with reference to the transmission standard signal, with image packet headers attached thereto. In a receiver side of the image packet communications system, a reception clock signal is generated subordinately synchronized to the reference clock signal, so that the reception clock signal is synchronized with the transmission clock signal.

Abstract: A bridge is disclosed for providing a connection between a MODBUS Plus network and an Ethernet network. The bridge includes a MODBUS circuit board, an Ethernet circuit board, and a CPU. The MODBUS circuit board is operably coupled to the local area network for receiving a message from an originating node having a five-byte routing path field. The CPU is operably connected to the circuit board for extracting a table location in response to a third byte within the routing path field. The Ethernet circuit board is operably connected to the CPU and the Ethernet network for forwarding the message to an IP destination in response to the table location.

Abstract: In a communication system including a local area network (LAN), first and second LAN telephone gateways connected to the LAN, a speech network, first and second private branch exchanges (PBXs) connected to the speech network and to the first and second LAN telephone gateways, respectively, and first and second telephone sets connected to the first and second PBXs, respectively, a first speech path is realized from the first telephone set via the first PBX to the first LAN telephone gateway. Then, it is determined whether a second speech path from the first LAN telephone gateway via the LAN, the second LAN telephone network and the second PBX to the second telephone set is possible or impossible. Then, after the second speech path is determined to be possible, the second speech path is realized. After the second speech path is determined to be impossible, a third speech path is realized from the first LAN telephone gateway via the first PBX, the speech network and the second PBX to the second telephone set.

Abstract: A large-scale fault tolerant asynchronous transfer mode (ATM) switch and a self-routing method in a 2n×n multiplexing switch.

Abstract: When a route hub receives device data synchronized with a device reference clock set in a source device connected to the route hub from the source device, the route hub modulates the device data to communication data synchronized with a transmission reference clock; adds a phase information to be used to demodulate the modulated communication data into the device data, to an empty area which is equivalent to a difference between a number of bits of each unit block of the device data and a number of bits of each unit block of the communication data synchronized with the transmission reference clock, at the time of the modulation.

Abstract: A method and apparatus for a handover of a communication signal (370) associated with a mobile communication unit (116) between a Generic C-based wireless communication system (302) and a MSC-based wireless communication system (304), is disclosed. The handover method includes establishing a plurality of trunks (401) between a landline switch (316) and a MSC (317). The method also includes configuring a landline number routing table (403) and a landline trunk group table (404) in the landline switch (316), a mobile trunk group table (406) in the MSC (317), and establishing a message translation table (405) in the computing platform (312), such that one of the plurality of trunks and an associated signaling path to the computing platform (312) are always selected when the handover is required.

Abstract: A receiving apparatus with intermittent receiving for receiving a TDMA SIG is disclosed. The receiving apparatus receives a FRQ reference SIG to control a voltage controlled OSC for generating a system clock and receives a TDMA synchronizing SIG to control the phase of a TDMA timing SIG to establish the reference FRQ synchronizing and the TDMA synchronizing. To save a power consumption in the sleep interval during the intermittent receiving, it is stopped to supply a supply power to a d/a converter supplied with the FRQ control data to supply a FRQ control voltage to the voltage controlled OSC. Just before an intermittent receiving interval, that is, the end of the sleep mode, the supply power to the d/a converter is supplied and the TDMA timing is compensated by calculation from the sleeping interval and the FRQ of the self-oscillation of the voltage controlled OSC.

Abstract: A multi-port switching device architecture decouples decode logic circuitry of each port of a network switch from its respective state machine logic circuitry and organizes the state machine logic as pools of transmit/receive engine resources that are shared by each of the decode logic circuits. Intermediate priority logic of the switching device cooperates with the decode logic and pooled resources to allocate frames among available resources in accordance with predetermined ordering and fairness policies. These policies prevent misordering of frames from a single source while ensuring that all ports in the device are serviced fairly.