Abstract: The invention concerns aluminum based alloys of the 7000 series with a high Young'3 s modulus (E.gtoreq.74 GPa), high mechanical strength (R.sub.0.2 .gtoreq.530 MPa in the longitudinal direction), good tenacity (KIC, longitudinal direction .gtoreq.20 MPa.sqroot.m ), and good resistance to corrosion under tension (.sigma..gtoreq.250 MPa in the short transverse direction, durability .gtoreq.30 days ASTM standard G 38-73. The alloy according to the invention is of the following composition by weight: from 5.5 to 8.45% of Zr; from 2 to 3.5% Mg; from 0.5 to 2.5% up to 0.5% Fe; up to 0.5% Si; other elements .ltoreq.0.05% each; and up to 0.15% in all with 0.1.ltoreq.Zr.ltoreq.0.5% 0.3.ltoreq.Cr.ltoreq.0.6%; and 0.3.ltoreq.Mn.ltoreq.1.1%. It is preferably worked by the following process steps: a solid body of the composition claimed above is formed by spray deposition; the body is converted to a worked product, at from 300.degree. to 450.degree. C.

Abstract: Hillock formation as a result of heating uncapped polycrystalline silicon layers can be avoided by first implanting the uncapped poly layers with silicon, oxygen, or nitrogen prior to heating. Equivalent mono-atomic oxygen or nitrogen doses in the range of about 10.sup.15 to about 5.times.10.sup.16 ions/cm.sup.2 at energies in the range 10-50 keV are useful with good results being obtained with equivalent oxygen doses of 2.times.10.sup.15 ions/cm.sup.2 at 30 keV. When polysilicon layers with this oxygen implant are heated to about 1150 degrees C., a temperature which would ordinarily produce pronounced hillock formation in un-capped, un-treated poly layers, it is found that hillock formation is suppressed. The implanted oxygen concentrations are far below what is required to produce a separate oxide layer or phase. Some effect on poly layer sheet resistance is observed for implanted oxygen but the implanted layers have sheet resistances within a factor of two of those without the oxygen implants.

Abstract: A method for manufacturing regions having adjustable uniform doping in silicon crystal wafers by neutron irradiation according to the reaction Si.sup.30 (n,.gamma.) Si.sup.31 .beta..sup.- P.sup.31 includes the steps of covering the silicon crystal wafer with neutron-absorbing materials of different thicknesses during the irradiation, and selecting materials having isotopes having a high absorption cross-section which yield stable isotopes in the nuclear reaction having small or short-lived activity. Suitable isotopes are B.sup.10, Cd.sup.113, Sm.sup.149, Gd.sup.155 and Gd.sup.157. The regions are generated photolithographically. By such specific material selection, very small layer thicknesses can be used and microfine surface zones or areas can be doped with high geometrical precision and large penetration depth. The method is particularly suited for manufacturing power thyristors.

Abstract: An ISL structure is fabricated by a process in which impurities are introduced into a semiconductor substrate (10) of first type conductivity (P) to form major and minor portions (18 and 18a) of a first region of opposite second type conductivity (N). The minor portion has a lower net impurity concentration than the major portion and extends to a considerably lesser depth. An impurity is introduced into the major and minor portions to form a second region (24) of first type conductivity. An impurity is introduced into the second region to form a third region (30) of second type conductivity spaced laterally apart from the minor portion. Metallization is then performed to create at least one Schottky rectifying contact (32) with the major portion and ohmic contacts (38, 36, and 34) with the substrate and second and third regions.

Abstract: A method of manufacturing a semiconductor device wherein a surface region of a semiconductor substrate is selectively heated by irradiation of a laser beam of a wavelength .lambda.. The method includes the steps of opening a window through an insulating layer formed on the surface of the semiconductor substrate, coating on the entire surface of the substrate a light transmitting film having an index n of refraction in such a manner that the thickness of the film over the exposed window part is equal, or substantially equal, to the value of .lambda./4n or .lambda./4n times an odd number, and then carrying out the irradiation of the laser beam. A photo-resist, thermally grown silicon dioxide film, silicon dioxide film by chemical vapor deposition, CVD phosphosilicate glass, or a glass film formed by coating hydroxide of silicon or its high molecule polymer is employed as the light transmitting film.

Abstract: A method for making semiconductor integrated circuits which improves and decreases fringing capacitance in semiconductor integrated circuits. An oxygenated, single-crystal silicon lamella is lightly doped, producing an excess of holes, thereby forming a semiconductor substrate. The substrate is used to fabricate semiconductor devices in the usual way, except that density may be slightly increased. After fabrication, the substrate is heated, preferably at 450.degree. C., until resistivity of the substrate has increased so that non-diffused regions of the substrate are substantially non-conductive.

Abstract: An austenitic stainless steel which is completely or practically completely austenitic in a hot worked, solution treated state, with properties characteristic for such steel and with a corrosion resistance clearly superior to the AISI 304 type of 18/8-steel, at least on a par with AISI 316 type of acid resistant steel 17/12-2Mo. The steel consists essentially of less than 0.10% C, less than 1.5% Si, between 0.10 and 0.30% Mn, between 17 and 20% Cr, between 6 and 16% Ni, between 2.0 and 4.0% Cu, less than 0.40% N, less than 1.0% Ti, less than 1.5% Nb and less than 100 ppm B, the balance being iron and impurities such as S, P and Mo usually present in steel.

Abstract: A process for forming a CIS (conductor-insulator-semiconductor) integrated circuit having one or more field-effect memory transistors, and one or more polysilicon resistors and/or polysilicon conductors. The polysilicon components are formed to predetermined sizes, as needed, so that the implant used to establish the memory threshold voltage of the transistor also provides the desired polysilicon resistance value(s). The process may be used to simultaneously form both memory and non-memory transistors.

Abstract: A process for preparing heat sensitive semiconductor switch which switches from OFF state to ON state at relatively low temperature.In a heat sensitive thyristor having PNPN four layer structure, an N type base region is exposed at one part of the surface exposed part in the P type base region to form an opening and ions of a P type impurity such as boron, aluminum and gallium are implanted from the opening to form a part having a large leakage current in a collector junction under excellent control, and to provide lower switching temperature for switching from the OFF state to the ON state with high reproducibility.

Abstract: In this process of producing a bipolar transistor, all the regions of the device except the emitter region are formed by ion implantation through an inorganic dielectric layer of uniform thickness. Subsequently, all the contact openings to the emitter, base and collector are formed and the emitter is implanted through the emitter contact opening. This unique combination of process steps permits the use of a surface insulating dielectric layer of uniform thickness, wherein all capacitances are uniform and controllable while still permitting direct implantation of the emitter, which, because of its shallow depth is difficult to implant through an oxide.

Abstract: A method of ion implantation is provided which is particularly applicable to the fabrication of integrated circuits with high current ion implantation apparatus utilizing ion beams having currents of at least 0.5 ma. The method avoids excessive charge buildup on semiconductor wafer surfaces which may destroy the surface electrical insulation, thereby rendering the integrated circuit ineffective. The method involves forming in a layer of electrically insulative material over the wafer, a plurality of openings through the insulative layer in the various chip areas to expose the semiconductor wafer surfaces which are to be ion implanted with conductivity-determining impurities, and in addition, forming openings through the insulative layer over the kerf area between wafer chips to expose wafer kerf adjacent to the chip openings. The total area exposed in the wafer kerf must be greater than the total area exposed in said chip wafer openings.