Patents Examined by Rupal C. Dharia
  • Controlling power up using clock gating
    Patent number: 5822596
    Abstract: During power up and power down of logic circuitry implemented in CMOS, the clock signal supplied to the logic circuitry is incremented and decremented, respectively, to avoid a sudden application or removal of the clock signal to the logic circuitry.
    Type: Grant
    Filed: November 6, 1995
    Date of Patent: October 13, 1998
    Assignee: International Business Machines Corporation
    Inventors: Humberto Felipe Casal, Hehching Harry Li, Trong Duc Nguyen, Nandor Gyorgy Thoma