Patents Examined by Russell Blum
  • Patent number: 5299197
    Abstract: A method for interactive transmission of information from one computer to others across communications channels. A computer server sends asynchronous packets of data based on requests from remote terminals. The packets are interpreted in a way that allows efficient transmission of text, pictures, menus, files, and programs.
    Type: Grant
    Filed: February 11, 1992
    Date of Patent: March 29, 1994
    Inventor: Roger Schlafly
  • Patent number: 5297145
    Abstract: A digital subscriber line circuit for connecting an ISDN subscriber to the trunk side of a digital exchange which comprises an SLD interface operating according to the SLD system. The subscriber line circuit further includes a transfer arrangement for transferring, during a transfer time window, data signals between incoming and outgoing time slots of the SL line of the SLD interface and time slots assigned thereto of outgoing or incoming trunks of the digital exchange. The subscriber line circuit comprises a slip detection means for detecting an incoming or outgoing trunk time slot slipping out of the transfer time window. The slip detection means controls a slip correction means which controls the transfer arrangement in response to the detection of a slip, so that data are skipped in one transfer direction and data are repeated in the other transfer direction.
    Type: Grant
    Filed: June 9, 1992
    Date of Patent: March 22, 1994
    Assignee: U.S. Philips Corporation
    Inventor: Gerardus M. J. Havermans
  • Patent number: 5280471
    Abstract: Interference in a high speed receive signal is effectively detected in a TDMA communications system wherein a plurality of time slots is provided within a TDMA frame. A comparator is arranged to receive a first signal indicative of receive signal strength and a reference level signal. The comparator compares the magnitudes of the two signals applied thereto and outputs a comparison result signal. A delay circuit is supplied with a second signal indicative of a time slot which is not in use and which delays the second signal by a predetermined time using a clock which is synchronized with the time slots of the TDMA frame. A gate circuit, preceded by the comparator and the delay circuit, is supplied with the outputs of the comparator and the delay circuit. The gate circuit outputs a third signal which changes a logic level in the event that the strength of the first signal exceeds that of the reference level signal during the time slot which is not in use.
    Type: Grant
    Filed: December 20, 1991
    Date of Patent: January 18, 1994
    Assignee: NEC Corporation
    Inventors: Seiji Kondou, Hiroshi Akahori
  • Patent number: 5280483
    Abstract: A call admission control system in an asynchronous transfer mode exchange includes a unit for describing attribute parameters of a call from the subscriber terminal; a unit for calculating, based on the attribute parameters, the average and the dispersion of the traffic speeds of the call; a unit for managing data of the average and the dispersion on each output route and data relating to each subscriber; and a unit for calculating the total average and the total dispersion of the data speeds on the selected output route; and a unit for calculating prediction values of cell abandon rate and end-to-end delay based on the average and the dispersion on the selected output route calculated by the total average and dispersion calculating unit, and for comparing the prediction values with the required service quality of cell discard rate and end-to-end delay, for determining whether or not the requesting call may be connected.
    Type: Grant
    Filed: August 9, 1991
    Date of Patent: January 18, 1994
    Assignee: Fujitsu Limited
    Inventors: Jyoei Kamoi, Hichiro Hayami, Yuji Kato, Toshio Shimoe, Shunji Abe, Michio Kusayanagi, Haruo Mukai, Toshio Soumiya
  • Patent number: 5274633
    Abstract: The present invention relates to a system switching system in an exchange system in which an ATM switch for exchanging asynchronous transfer mode (ATM) cells is duplexed. In order to switch between ATM switches accurately with drop-out and overlap of cells eliminated, at the input side of the ATM switches, a bit indicating active is inserted into the header of a cell from a transmission line for application to the switch in the active system and a bit indicating standby is inserted into the header of a cell for application to the switch in the standby system and, at the output side of the ATM switches, bits in the headers of cells output from respective switches are referred to and only active indicating cells are selected to be output to a transmission line. Buffers for storing active indicating cells are provided at the outputs of the ATM switches, respectively.
    Type: Grant
    Filed: July 29, 1991
    Date of Patent: December 28, 1993
    Assignee: Fujitsu Limited
    Inventors: Yumiko Kato, Satoshi Kakuma, Yasuhiro Aso, Yoshihiro Uchida, Hiroshi Miyake
  • Patent number: 5267231
    Abstract: A differential protective relay system includes protective relays 19A and 19B at the terminals of a protected transmission line segment 21. Analog signals QL1 and QL2 are sampled at the respective ends of the protected line segment 21, digitally encoded using delta modulation and biphase-mark encoding, multiplexed and transmitted over a 1.544 Mbps T1 communication channel 20 to the other end of the line where they are decoded and compared with the local signal at that end. Power is removed from the protected line segment if the difference between the local and remote signals exceeds a predefined value. Biphase-mark encoding is employed so that a clock signal may be recovered from the decoded signals.
    Type: Grant
    Filed: July 3, 1991
    Date of Patent: November 30, 1993
    Assignee: ABB Power T&D Company Inc.
    Inventor: Janusz W. Dzieduszko
  • Patent number: 5265089
    Abstract: A digital multiplex communication system for carrying out digital multiplex communication between a plurality of terminal stations, at least two including one initiating party and the other party to communicate with, via a branching unit. In this system, groups of bits in a communication frame are allocated in advance for use in communication between one party and the other. In order to diagnose the state of the transmission line to the other party including the branching unit, loopback setting signals for setting the other party in the loopback test mode and loopback test signals are inserted into specific bit positions of the preallocated groups of bits in performing communication.
    Type: Grant
    Filed: January 21, 1993
    Date of Patent: November 23, 1993
    Assignee: NEC Corporation
    Inventor: Akifumi Yonehara
  • Patent number: 5243594
    Abstract: A method for transmitting message blocks between transmission lines of a communication processor including those transmission lines being allocated to one another in existing connections involves, in a communication processor system, line connecting units connected with the transmission lines which are to be connected to a plurality of switching processors via at least one internal bus system. In conjunction with existing connections, a flow control provides for the transmission of message blocks between the line connecting units and the switching processors. This cause, given a momentary overload of one of the switching processors, or one of the outgoing transmission lines, only those message blocks determined for a particular switching processor or those for the outgoing transmission lines are temporarily put on hold for a transmission.
    Type: Grant
    Filed: September 4, 1991
    Date of Patent: September 7, 1993
    Assignee: Siemens Aktiengesellschaft
    Inventors: Bernd Dasch, Robert Naessl
  • Patent number: 5235594
    Abstract: In a switching system for voice input/output devices, voice data is sampled, e.g., at an 8 KHz rate. To minimize overhead, the maximum number of devices in a system have a time slot for outputting data. Thus, the system operates at a system clock rate of 8 KHz times the maximum number of devices to be supported. In the illustrated embodiment, 768 devices are supported and thus the system operates at a 6.144 MHz clock rate. To enable such a large number of devices to be supported at a relatively slow clock rate, the data is transmitted in parallel. The switching system is constructed as N buckets or cabinets of M processing modules, each connected to J devices. A bus controller for each bucket connects the multiprocessing system bus in that bucket to intersystem buses connected to bus controllers in adjacent cabinets. Voice data samples are collected by a module collection bus and transferred to a bucket collection bus following data from any preceding buckets.
    Type: Grant
    Filed: August 9, 1991
    Date of Patent: August 10, 1993
    Assignee: Westinghouse Electric Corp.
    Inventor: Paul O. Lee
  • Patent number: 5233601
    Abstract: The invention provides a method of measuring the load of a communication system, and more particularly of a multiplex switching network for asynchronous cells or packets. Each cell transmitted on the multiplex has a registered value which is divided by a predetermined number (N). The value forms the first operand (E2) of a subtraction and the result of the division forms the second operand (E1). A predetermined value is added to the result of the subtraction when the heading of the transmitted cell contains a particular identifier. A zero value is added in the contrary case. The result of the subtraction followed by the addition constitutes the new value which is to be recorded, which likewise represents the measurement of the load. The identifier identifies, for example, an occupied cell or a cell belonging to a given virtual circuit. A circuit for implementing the method is likewise described.
    Type: Grant
    Filed: May 17, 1991
    Date of Patent: August 3, 1993
    Inventors: Pierre Boyer, Michel Servel, Didier Tranchier
  • Patent number: 5229994
    Abstract: A bridge for connecting an IEEE 802.3 local area network to an asynchronous time-division multiplex telecommunication network comprises a part implementing the functions of layer 2.1 of an asynchronous time-division multiplex telecommunication network transmission protocol and a part which is a conventional local area network interface implementing the functions of layer 1 of the local area network data transmission protocol. The circuit is applicable to the transmission of data between different local area networks.
    Type: Grant
    Filed: September 27, 1991
    Date of Patent: July 20, 1993
    Assignee: Alcatel Cit
    Inventors: Jean-Michel Balzano, Yvon Noslier
  • Patent number: 5208808
    Abstract: A timeslot assigning circuit for use in a UCOL-type star network includes a first circuit block having a RAM-type memory for storing incoming requests for assignment. The first circuit block is connected to a second circuit block, which includes a FIFO memory in which requests for assignment are cyclically loaded. A decrementing circuit is connected downstream from the FIFO memory, and a filter is connected at the input of the FIFO memory and downstream on the decrementing circuit, so that requests for assignment which are null or are already satisfied are eliminated. A control circuit permits the cyclic scanning of requests, while a second FIFO memory is provided at the output of the first FIFO memory to contain the requests relative to single slots assigned during an operating cycle.
    Type: Grant
    Filed: September 24, 1991
    Date of Patent: May 4, 1993
    Assignee: Alcatel, N.V.
    Inventors: Franco D'Ignazio, Bruno Bianchi
  • Patent number: 5204857
    Abstract: An ATM exchange system capable of accommodation not only terminals of an ATM system but also terminals of an STM system at low cost. The ATM system includes an ATM channel switch for providing a direct exchange connection between the ATM terminal and an ATM trunk line, an STM channel switch for providing a direct exchange connection between the STM terminal and an STM trunk line, and an STM/ATM conversion module connected between the ATM channel switch and the STM channel switch and adapted to convert a call of one system to that of another system when a call is made between ATM terminal/line and STM terminal/line.
    Type: Grant
    Filed: August 20, 1991
    Date of Patent: April 20, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keiichi Obara
  • Patent number: 5200957
    Abstract: The invention relates to a method for communication and handoff in a cellular mobile radio system and a base station and a mobile station for communication and handoff in such a system, in which time slot identifier codes are transmitted in bursts in times slots in frames of radio channels used for time division communication channels, the time slot identifier codes being indicative of burst time slot in a frame but not of transmitter or receiver entity or radio channel, the time slot identifier codes being used for burst synchronization and determining bursts the signal strength of which to be measured for the purpose of possible handoff.
    Type: Grant
    Filed: July 22, 1991
    Date of Patent: April 6, 1993
    Assignee: Telefonaktiebolaget L M Ericsson
    Inventor: Jan E. A. S. Dahlin
  • Patent number: 5177740
    Abstract: Frame/slot synchronization is applied to a received Time Division Multiple Access (TDMA) signal and a temporal position of a reference feature is acquired, such as a synchronizing bit stream or preamble, associated with a desired time slot. The desired time slot is but one of a plurality of time slots that comprise a frame. Verification that the acquired temporal position corresponds to the desired time slot is performed by repetitively estimating a temporal position of the reference feature in a subsequent frame and sampling the subsequent frame at the estimated temporal position to determine if the reference feature is present. The temporal position of the reference feature of the desired time slot relative to the frame is maintained over a plurality of received frames.
    Type: Grant
    Filed: September 3, 1991
    Date of Patent: January 5, 1993
    Assignee: General Electric Company
    Inventors: Raymond L. Toy, Sandeep Chennakeshu
  • Patent number: 5177736
    Abstract: A packet switch comprises a switch having a plurality of input lines and a plurality of output lines for sending a packet supplied from each of the input lines to one of the output lines selected in accordance with routing information attached to each packet, a plurality of pairs of input/output lines connected to terminals or other switches, a plurality of line interface provided one for each of the input/output lines and each connected to one of the input lines and one of the output lines of the switch, and a controller connected to one of the input lines and one of the output lines of the switch. Control information is communicated between the controller and the line interfaces or the switch via a control packet through the switch. The switch may be a plurality of multi-stage connected unit switches and input lines and output lines thereof are divided into a plurality of groups.
    Type: Grant
    Filed: February 4, 1991
    Date of Patent: January 5, 1993
    Assignees: Hitachi Ltd., Hitachi Software Engineering Co., Ltd.
    Inventors: Shiro Tanabe, Akinori Kubo, Yoshiaki Kihara
  • Patent number: 5155725
    Abstract: A token ring network in which the token release mechanism adapts to the status of the other stations in the ring. Rather than releasing the token at the end of the token holding period, the token-holding station requests permission to continue transmitting. If permission is not denied by another station desiring to use the network, the token-holding station continues to transmit without interruption. Both absolute and relative priority can be accommodated with this adaptive token release mechanism. The permission denied message preferably comprises a simple modification of the request for permission to continue message.
    Type: Grant
    Filed: January 3, 1991
    Date of Patent: October 13, 1992
    Assignee: Bell Communications Research, Inc.
    Inventor: Khalid M. Khalil
  • Patent number: 5144621
    Abstract: In a common bus communication system in which multiple bus interfaces (2) are connected to the common bus, each bus interface comprises a main memory (21) and an auxiliary memory (28, 29). When a packet destined to the own interface is detected by an address detector (22), memory control data is stored into the auxiliary memory in a location corresponding to a destination user terminal (5.sub.i) as well as to the location of the packet in the main memory. When a read request is received from the destination user terminal, control data is fetched from the auxiliary memory and a packet in the data memory is accessed according to the fetched control data, and a copy of the accessed packet is sent to the destination user terminal, and following the transmission the control data is updated. Packets propagating along the common bus are stored into the main memory according to the updated control data.
    Type: Grant
    Filed: September 27, 1991
    Date of Patent: September 1, 1992
    Assignee: NEC Corporation
    Inventors: Haruhiko Kinashi, Toshiyuki Watanabe