Abstract: A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.

Abstract: An information handling system for mirroring data, in a fashion that is similar to asynchronous mirroring, but less complex in function. Source data storage for storing and updating data is provided, with first intermediate data storage, target data storage, second intermediate data storage, and mirroring control. The mirroring control conducts first cyclic incremental flashcopy of the source data storage, the beginning of each first cyclic incremental flashcopy comprising a consistency point. The first cyclic incremental flashcopy comprises copying data to be mirrored to the first intermediate storage and synchronously mirroring the data to the second intermediate data storage.

Abstract: The invention relates to a reproduction apparatus having a buffer for reducing the mean access time to an information carrier which has for example a discontinuous data structure or a relatively long access time. For writing sectors to the buffer and for finding sectors in the buffer, a control table with a number of place holders and three variables is provided, the place holders in each case pointing with an index to a subsequent place holder in an endless chain of place holders which is divided into three regions, in which a predetermined sector in the order in the respective region is identified by one of the variables. Even though only one row of place holders is provided, multiple access to a plurality of sectors written to the buffer is made possible with a low outlay by means of the control table, so that the number of slower accesses to the information carrier is reduced and the mean access time is shortened.

Abstract: When shifting the condition of a pair of a main volume and a sub-volume from a split condition to a pair condition according to a request from a user, an information processing unit which can access the sub-volume is inquired whether it mounts the sub-volume or not. As a result, if a managing computer receives a notice from the information processing unit that it mounts the sub-volume, the managing computer displays a warning on its display. Thereby, data on the sub-volume can be prevented from being erased by an operation mistake of the user.

Abstract: One embodiment of the present invention includes a method for enabling a client node to automatically read ahead data from a network based file system. Specifically, in response to an application operating on the client node requesting a data page, the client node requests delivery of data pages from the network based file system. Upon reception, these data pages can each be served to the application. After each data page is served, it is determined whether the number of unrequested available data pages is less than the value of M. If so, an asynchronous read-ahead request is sent to a primary node of the network based file system for P number of data pages. The values of M and P can be such that P data pages can be fetched before M data pages are consumed by the requesting application.

Abstract: The disclosed embodiments provide for a system and method for storing data in a flash memory device that has a code bank and a data bank. The method includes writing data to the data bank under control of a flash driver in the code bank when sufficient space is expected to exist in the data bank. Otherwise, the method includes writing data to the code bank under control of a flash driver in a storage device that is external to the flash memory device.

Abstract: A variable latency cache memory is disclosed. The cache memory includes a plurality of storage elements for storing stack memory data in a first-in-first-out manner. The cache memory distinguishes between pop and load instruction requests and provides pop data faster than load data by speculating that pop data will be in the top cache line of the cache. The cache memory also speculates that stack data requested by load instructions will be in the top one or more cache lines of the cache memory. Consequently, if the source virtual address of a load instruction hits in the top of the cache memory, the data is speculatively provided faster than the case where the data is in a lower cache line or where a full physical address compare is required or where the data must be provided from a non-stack cache memory in the microprocessor, but slower than pop data.

Abstract: The bus controller of a bus system supports isochronous messages and non-isochronous messages for which the bus system does and does not support a guaranteed transceiving capacity per time-frame respectively. The system has a first and second memory section for exchange of data from the isochronous messages between a processor and the bus controller. The bus controller has access priority over the processor in alternating first and second ones of the time frames. The bus controller transfers data from isochronous messages between the bus medium and the first and second memory section in the first and second ones of the time frames respectively. The processor has access priority to the first and second memory section over the bus controller in the second and first ones of the time frames respectively.

Abstract: A method to control access to logical volumes disposed in an information storage and retrieval system using parallel access volumes. The method provides an information storage and retrieval system comprising a plurality of logical volumes, and a plurality of host computers, where each host computers is capable of communicating with the information storage and retrieval system. The method creates a parallel access volume having an alias, and persistently associates that parallel access volume with an original base logical volume, where the original base logical volume may be assigned to one of (N) logical volume groups. If the original base logical volume is assigned to the (i)th logical volume group, the method permits each host computers assigned to the (i)th host computer group to access the original base logical volume, or the current base logical volume, associated with the parallel access volume.

Abstract: A stack cache memory in a microprocessor and apparatus for performing fast speculative pop instructions is disclosed. The stack cache stores cache lines of data implicated by push instructions in a last-in-first-out fashion. An offset is maintained which specifies the location of the newest non-popped push data within the cache line stored in the top entry of the stack cache. The offset is updated when an instruction is encountered that updates the stack pointer register. When a pop instruction requests data, the stack cache speculatively provides data specified by the offset from the top entry to the pop instruction, before determining whether the pop instruction source address matches the address of the data provided. If the source address and the address of the data provided are subsequently determined to mismatch, then an exception is generated to provide the correct data.

Abstract: A manager is allowed to retrieve management information of a logical volume for which the manager has the management right. A storage system has multiple logical volumes managed by different managers and a controller controlling the multiple logical volumes. The storage system stores first identification information for identifying each of the multiple logical volumes, first management information of a logical volume mapped to the first identification information, and correspondence between the first identification information and manager identification information of a manager having a management right for a logical volume identified by the first identification information.

Abstract: A cache memory for performing fast speculative load operations is disclosed. The cache memory caches stack data in a LIFO manner and stores both the virtual and physical address of the cache lines stored therein. The cache compares a load instruction virtual address with the virtual address of the top cache entry substantially in parallel with translation of the virtual load address into a physical load address. If the virtual addresses match, the cache speculatively provides the requested data to the load instruction from the top entry. The cache subsequently compares the physical load address with the top cache entry physical address and if they mismatch, the cache generates an exception and the processor provides the correct data. If the virtual and physical load addresses both miss in the stack cache, the data is provided by a non-stack cache that is accessed substantially in parallel with the stack cache.

Abstract: A storage system having disk drives, a first and a second cache memory for temporarily storing data sent from a host system so as to be written in the disk drives and a duplicate of the data, a first FIFO buffer for temporality storing the duplicate data in order to transfer the duplicate data from the first cache memory to the second cache memory, and a second FIFO buffer for temporality storing the duplicate data in order to transfer the duplicate data from the second cache memory to the first cache memory. In the case where the data sent from the host system so as to be written in the disk drives are temporarily stored in the first cache memory and the duplicate of the data is stored in the second cache memory, completions of the data writing are reported to the host system at the time point when the data and the duplicate data are stored in the fist cache memory and the second cache memory.

Abstract: Disclosed is a symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors within a partition to complete concurrently. Thus, a global TLB lock, synchronization, and TLB unlock is not necessary. When a TLBI instruction is executed, the master dynamically manages the behavior of the TLBI operation based on asynchronously snooping another TLBI. If concurrent TLBI management is required, then the master dynamically degrades the TLBI to a “barrier” class instruction.

Abstract: Methods, system and computer program product are provided to improve the efficiency of data transfers in a PPRC environment. A block of data to be transferred is divided into tracks. Each track is allocated to a data mover task control block (TCB) with a master TCB being assigned to supervise the data mover TCBs. The tracks are then transferred from the primary storage controller to the secondary controller in a piped fashion over a link coupling the primary and secondary storage controllers. However, the usage of resources is monitored by a resource management algorithm and, if too many TCBs are being used for a transfer or if the supply of data mover TCBs is exhausted, the transfer is automatically switched to a serial, non-piped transfer with the master TCB serving as the data mover TCB for the remaining tracks. In addition, the various links coupling the primary and secondary storage controllers is monitored to determine which link will provide the fastest transfer.