Abstract: The present invention discloses a programmable logic device with on-chip user non-volatile memory, comprising: a programmable logic array, which is a user programmable logic array and comprises a SRAM array and a logic block array with an interface; the SRAM array is used to store configuration data to control the logic block array in real time, therefore, the logic block can be formed to perform the function a user desires; a non-volatile memory block, comprising one or more segments storing configuration data and one or more segments storing user data which is used during FPGA's normal operation after configuration; the non-volatile memory block has only one interface, and the non-volatile memory block connects to a programming controller through the interface; a programming controller, which can randomly access the non-volatile memory through a data bus, an address bus, and corresponding control signals.

Abstract: A system includes a solid-state storage array having a plurality of solid-state storage devices and a storage controller coupled to the solid-state storage array, the storage controller including a processing device, the processing device to select a segment height based on erase block sizes of the plurality of solid-state storage devices. The processing device is further to program a data segment using the segment height to a data stripe across two or more of the plurality of solid-state storage devices and store the segment height in metadata associated with the data segment.

Abstract: Aspects of the disclosure relate to directing and tracking translation lookaside buffer (TLB) shootdowns within hardware. One or more processors, comprising one or more processor cores, may determine that a process executing on a processing core causes one or more virtual memory pages to become disassociated with one or more previously associated physical memory addresses. The processing core which is executing that process which caused the disassociation may generate a TLB shootdown request. The processing core may transmit the TLB shootdown request to the other cores. The TLB shootdown request may include identification information, a shootdown address indicating the disassociated virtual memory page or pages which need to be flushed from the respective TLBs of the other cores, and a notification address indicating where the other cores may acknowledge completion of the TLB shootdown request.

Abstract: Container-image layers can be managed. For example, a computing device can determine a first score for a first layer of a container image and a second score for a second layer of the container image. The computing device can determine that the first score corresponds to a first storage destination among several possible storage destinations. The computing device can also determine that the second score corresponds to a second storage destination among the possible storage destinations. The second storage destination can be different from the first storage destination. The computing device can then store (i) the first layer in the first storage destination based on the first layer being correlated to the first score, and (ii) the second layer in the second storage destination based on the second layer being correlated to the second score.

Abstract: Examples of techniques for sensitive data redaction in a memory dump are described herein. An aspect includes, based on a dump of a virtual address space being triggered, receiving a primary dump corresponding to the virtual address space, the primary dump including one or more tagged memory pages. Another aspect includes identifying, by a sensitive data identification module, sensitive data that is located outside of the of the one or more tagged memory pages in the primary dump. Another aspect includes redacting data corresponding to the sensitive data and the one or more tagged memory pages to determine a redacted dump.

Abstract: A memory system includes a memory device including a main memory and a cache memory that includes a plurality of cache lines for caching data stored in the main memory, wherein each of the cache lines includes cache data, a valid bit indicating whether or not the corresponding cache data is valid, and a loading bit indicating whether or not read data of the main memory is being loaded; and a memory controller suitable for scheduling an operation of the memory device with reference to the valid bits and the loading bits.

Abstract: A method for accessing a storage system, the method may include receiving a block call, from a processor that executes an application and by a storage engine of a computer that is coupled to a storage system; generating, by the storage engine and based on the block call, a key value call; and sending the key value call to a key value frontend of the storage system.

Abstract: A scheme referred to as a “Region-based cache restoration prefetcher” (RECAP) is employed for cache preloading on a partition or a context switch. The RECAP exploits spatial locality to provide a bandwidth-efficient prefetcher to reduce the “cold” cache effect caused by multiprogrammed virtualization. The RECAP groups cache blocks into coarse-grain regions of memory, and predicts which regions contain useful blocks that should be prefetched the next time the current virtual machine executes. Based on these predictions, and using a simple compression technique that also exploits spatial locality, the RECAP provides a robust prefetcher that improves performance without excessive bandwidth overhead or slowdown.

Abstract: One embodiment provides a method comprising receiving an input data stream, partitioning the input data stream into a plurality of data blocks, and compressing the data blocks utilizing a plurality of processor sets. Each processor set is assigned a data block to compress. The processor sets compress in parallel to exploit inter-block parallelism. Each processor set comprises one or more processors that collaborate in compressing an assigned data block to exploit intra-block parallelism. The method further comprises writing a plurality of compressed data blocks resulting from the compressing to a storage device in encoded form.

Abstract: Example tiered storage systems, storage devices, and methods provide tier configuration by peer storage devices. Each tiered storage device is configured to communicate with a plurality of peer storage devices with storage device identifiers. The storage devices may query each other for performance characteristics and/or self-assigned performance tiers and organize the storage devices into a tier configuration. Each storage device, a storage controller, another system, and/or some combination may store metadata that describes the tier configuration. The tier configuration may then be used to route host data commands among the plurality of peer storage devices.

Abstract: The present disclosure includes apparatuses and methods for computing reduction and prefix sum operations in memory. A number of embodiments include processing circuitry configured to compute a reduction operation on data stored in a group of memory cells by splitting the data into a plurality of elements, copying each of the plurality of elements into elements that are wider than before being copied, and performing a logical operation associated with the reduction operation on each of the copied elements.

Abstract: Examples include techniques for emulating a non-volatile dual inline memory module (NVDIMM) in a computing platform using a non-volatile storage device. When a power up event occurs for the computing platform, a host memory buffer may be allocated in a system memory device and a backing store for the host memory buffer may be copied from the non-volatile storage device to the host memory buffer in the system memory device. When a power down event or a flush event occurs for the computing platform, the host memory buffer may be copied from the system memory device to the corresponding backing store for the host memory buffer in the non-volatile storage device. Thus, virtual NVDIMM functionality may be provided without having NVDIMM hardware in the computing platform.

Abstract: A data storage device can have one or more timestamps to indicate chronological information associated with data stored in the data storage device. A controller may be connected to a timestamp module and a transducing head to allow a timestamp to be written to a magnetic data storage medium as directed by the timestamp module. The timestamp can consist of chronological information relating to user-generated data stored on the data storage medium.

Abstract: A memory system includes a memory device comprising a plurality of memory cells storing data, and configured to perform one or more of a write operation, read operation and erase operation on the plurality of memory cells; and a controller configured to control an operation of the memory device, wherein the controller is configured to: cache a logical block addressing (LBA) mapping table from the memory device when the memory system is powered on by driving power applied thereto; and transfer a direct memory access (DMA) setup to a host when the LBA mapping table is cached.

Abstract: Causing data in an in-band storage device coupled to a host computing system to be transferred to an out-of-band (OOB) storage device includes coupling the in-band storage device to the OOB storage device, the in-band storage device detecting commands from the host computing system to transfer the data in the in-band storage device to a cloud storage, and the in-band storage device transferring the data in the in-band storage device to the to the OOB storage device in response to receiving a command from the host computing system to transfer the data in the in-band storage device to the cloud storage. The OOB storage device may be coupled to the cloud storage. Causing data in an in-band storage device to be transferred to an OOB storage device may also include causing data stored at the OOB storage device to be transferred to the cloud storage.

Abstract: In one embodiment, an apparatus includes: a page table circuit to receive a virtual address and to generate at least a portion of a physical address therefrom; and a mapping rule table coupled to the page table circuit, the mapping rule table to receive mapping metadata of a page of a system memory and, based on the mapping metadata, output a mapping rule for the page. Other embodiments are described and claimed.

Abstract: Systems, devices, and methods for data transfer between memory devices on a shared bus are provided. In one aspect, a system includes first and second memory devices and a shared bus. A host device is configured to send at least one control signal through the shared bus to the first and second memory devices, and the control signal specifies data to be transferred from the first memory device to the second memory device. In response to receiving the control signal, the first memory device is configured to read and transmit the data to the shared bus, and the second memory device is configured to receive the data from the shared bus and write the data in the second memory device. The data is transferred directly from the first memory device to the second memory device through the shared bus without passing through the host device.

Abstract: Techniques are provided for service-level rebuild of one or more storage drives. Storage drives can store data of varying priority levels. In an example, when a storage drive is rebuilt, higher-priority data is written to the rebuilt storage drive before lower-priority data. In some examples where multiple storage drives are being rebuilt, a system can prioritize a use of rebuild bandwidth in rebuilding storage drives.

Abstract: The present teaching relates to a method, system, and programming for determining a source of a data object. A first average latency of a plurality of users in accessing the data object from the first data source is computed, wherein the first data source was previously identified as being the source of the data object. From each of other data sources, a second average latency of the plurality of users in accessing the data object from the other data source is obtained. In response to the first data source satisfying a first criterion associated with the first average latency, the first data source is maintained to be the source of the data object. In response to the first data source violating the first criterion, one of the other data sources that satisfies a second criterion associated with the second average latency is deemed as the source of the data object.

Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data from a host system, and writing the data into a plurality of first physical programming units; performing a multi-frame encoding according to the plurality of data to generate encoded data, and writing the encoded data into a second physical programming unit; and writing a plurality of first concatenated information related to the encoded data into the plurality of first programming units, respectively.