Patents Examined by Ryan Johnson
  • Patent number: 12218656
    Abstract: Provided is a driving apparatus including a temperature detection circuit configured to output a temperature detection signal corresponding to a temperature of a switching device, a current detection circuit configured to sample, at a timing during an ON period of the switching device, a current detection signal corresponding to a current that flows in the switching device, and a driving circuit configured to adjust, according to the temperature detection signal and the current detection signal, a driving current to be supplied to a control terminal of the switching device. When the current detection signals are the same, the driving circuit may decrease the driving current according to the temperature detection signal indicating a lower temperature of the switching device. When the temperature detection signals are the same, the driving circuit may decrease the driving current according to the current detection signal indicating a smaller current regarding the main current.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: February 4, 2025
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masashi Akahane
  • Patent number: 12218662
    Abstract: A line driver circuit include a multitude of PMOS and NMOS transistors. A first PMOS transistor receives an output voltage of a first level converter. A second PMOS transistor receives a first reference voltage. A third and fourth PMOS transistors receive an output voltage of a second voltage level converter. The source terminal of the first PMOS transistor receives the supply voltage. The drain terminal of the fourth PMOS transistor is coupled to an output terminal of the line driver circuit. A first NMOS transistor receives an input signal. A second NMOS transistor receives a second reference voltage. A third and fourth NMOS transistors receive an output voltage of a third level converter. The first NMOS transistor receives a ground potential. The drain terminal of the fourth NMOS transistor is coupled to the output terminal of the line driver. The first, second and third voltage converters receive the input signal.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: February 4, 2025
    Assignee: Synopsys, Inc.
    Inventors: Tigran Petrosyan, Arshavir Matevosyan, Davit Vanetsyan, Davit Petrosyan, Ashot Muradyan
  • Patent number: 12218508
    Abstract: An electrical generator that is configured to simultaneously output different types of electrical power so that electrically powered components that require different types of electrical power can be simultaneously powered by the electrical generator. The electrical generator can be used at any location where electrically powered components that require different types of electrical power are utilized. Instead of or in addition to outputting different types of electrical power, the electrical generator can also be configured to output at least one type of electrical power as well as a cooling liquid for use in cooling an external heat generating component.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: February 4, 2025
    Assignee: LaValley Industries, LLC
    Inventors: Jason Lavalley, Douglas Coutlee, Daniel Larson, Marc Annacchino, Don Peet
  • Patent number: 12218657
    Abstract: The present invention provides a Miller clamping device for parallel switching transistors and a driver comprising the same. The Miller clamping device includes: a driver chip including an output terminal and a built-in Miller clamping circuit with a Miller clamping terminal, the output terminal of the driver chip being configured to output a pulse width modulation signal; and a plurality of auxiliary Miller clamping circuits, each of the auxiliary Miller clamping circuits being connected between a gate of a corresponding switching transistor and the Miller clamping terminal of the built-in Miller clamping circuit. When the built-in Miller clamping circuit is triggered for Miller clamping, a Miller current generated by the corresponding switching transistor flows to a first direct-current (DC) voltage through a corresponding auxiliary Miller clamping circuit. The Miller clamping device of the present invention can perform Miller clamping on the parallel switching transistors and reduce the circuit cost.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: February 4, 2025
    Assignee: SANTAK ELECTRONIC (SHENZHEN) CO., LTD.
    Inventors: Dongxin Jin, Huafen Ouyang, Lei Cao, Hualiang Li, Dawei Zheng
  • Patent number: 12218513
    Abstract: A power transfer device including an AC power source unit and a single power transfer element, and a power reception device including a single power reception element electrically coupled to the power transfer element and a power reception circuit outputting power are included. The power reception circuit includes a different potential field disposed at a position that is an electric field formed by the power transfer element and at which intensity of the electric field is different from intensity of an electric field formed at a position of the power reception element.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: February 4, 2025
    Assignee: THE UNIVERSITY OF TOKYO
    Inventors: Shinichi Warisawa, Yen Po Wang, Munemasa Sugimoto
  • Patent number: 12212153
    Abstract: This disclosure provides systems, methods and apparatuses for wireless power transmission and reception. A wireless power transmission apparatus may include a primary coil that transmits power to a corresponding secondary coil in a wireless power reception apparatus. The wireless power transmission apparatus may configure characteristics of the wireless power transmission based on a load setting of a wireless power reception apparatus. The wireless power transmission apparatus may take into account a coupling factor and power transfer characteristics of the wireless power reception apparatus in determining a configuration of the wireless power transmission from the wireless power transmission apparatus to the wireless power reception apparatus. In some implementations, a change in wireless power transmission may occur based on a corresponding change in the load. For example, the change in wireless power transmission and the corresponding change in the load may occur in relation to a synchronization event.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: January 28, 2025
    Assignee: Dolby Laboratories Inc.
    Inventors: Jayanti Ganesh, Viswanathan Kanakasabai, Suma Memana Narayana Bhat, Joginder Yadav
  • Patent number: 12212310
    Abstract: An electronic device includes a GaN power FET, a GaN driver coupled to the GaN power FET and a gate bias circuit coupled to the GaN driver. The GaN power FET and the GaN driver are monolithically integrated on a single GaN die. The gate bias circuit is predominately monolithically integrated on the single GaN die and includes only one active component external to the single GaN die. In one embodiment, the only active component external to the single GaN die is a linear regulator. In another embodiment, the only active component external to the single GaN die is a shunt regulator. In yet another embodiment, the only active component external to the single GaN die is a Zener diode.
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: January 28, 2025
    Inventors: Manish Shah, Rajesh Ghosh, Syed Asif Eqbal, Firdos Khan, Subhendu Rana
  • Patent number: 12212141
    Abstract: A power conversion device inputs or outputs a power for changing a state quantity of a distribution grid to which a voltage source device is connected, to or from the distribution grid. A grid control unit calculates a power command value of the power conversion device such that a drooping characteristic is provided for compensating for a deviation from a control target of the state quantity obtained from an output of a detector. A frequency characteristic of control computation for calculating a power command value from the deviation in the system control unit is defined such that a first control gain value in a first frequency range including direct current is set corresponding to a slope of the drooping characteristic, and a second control gain value in a second frequency range including higher frequencies than the first frequency range is set to be lower than the first control gain value.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: January 28, 2025
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuki Itogawa, Sadayuki Inoue, Tomihiro Takano, Keishi Matsuda, Xiaowei Dui
  • Patent number: 12212229
    Abstract: A static transfer switch is provided for supplying power to a load alternately from two different power sources. Preferably, switching between the two power sources occurs within one electrical cycle. In order to control inrush currents and reduce disruption during power transfers between the two power sources, switches are provided to configure which input phases are connected to the output phases.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: January 28, 2025
    Assignee: ABB SCHWEIZ AG
    Inventors: Adil Oudrhiri, Debrup Das, Zhiguo Pan
  • Patent number: 12206395
    Abstract: Multi-way signal switch designs and methods for reducing parasitic capacitance. In a first embodiment, two or more series-coupled FET shunt-switches are coupled to at least one switch cell through-switch. At least one shunt-switch is set to an OFF state during normal operation so as to function as a capacitor, while at least one other shunt-switch is set to behave like a capacitor in a switch cell ON state, and is set to behave like a resistor in a switch cell OFF state. In a second embodiment, the combination of at least one FET shunt-switch coupled in series with a capacitor functions as a shunt connection for the signal path, wherein the FET shunt-switch is set to behave like a capacitor when the switch cell is in an ON state, and is set to behave like a resistor when the switch cell is in an OFF state.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: January 21, 2025
    Assignee: pSemi Corporation
    Inventors: Yucheng Tong, Parvez H. Daruwalla
  • Patent number: 12206391
    Abstract: A bootstrapping gate driver circuit in which the size of the bootstrap capacitors is reduced. The gate-to-source voltage of the high side (pull-up) FET is pre-driven to an initial voltage (pre-driven voltage) before the bootstrap capacitor releases charge to charge up the gate-to-source voltage of the high side FET. This pre-driven voltage is applied through a pre-driven FET that allows current flow from the supply voltage to charge the gate of the high side FET to the pre-driven voltage. The pre-driven FET is turned on by a turn-on signal that occurs before the bootstrap capacitor releases charge. The pre-driven period (and hence, the pre-driven voltage) is determined from the time that the pre-driven FET begins to turn on, to the time that the bootstrap capacitor starts to release charge.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: January 21, 2025
    Assignee: Efficient Power Conversion Corporation
    Inventors: Edward Lee, Ravi Ananth, Michael Chapman
  • Patent number: 12206402
    Abstract: A control unit has an input with a positive and negative connectors. The control unit also includes an output and with an electronic switch. The switch has a first connector, a second connector and a control connector, and has an on-state resistance between its first and second connector that depends on a control voltage at the control connector of the switch. The first connector is connected to the connector for the positive potential of the input, the second connector is connected to the connector for the positive potential of the output, and the control connector is connected to a trigger circuit. A second controllable switch is also included with a first connector connected to the second connector of the first switch, a second connector connected to the control connector of the first switch, and a control connector connected to the connector for the negative potential of the input.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: January 21, 2025
    Assignee: Hella GmbH & Co. KGaA
    Inventors: Jan Frederik Buthke, Jan Schmaeling, Martin Strauch
  • Patent number: 12206398
    Abstract: Various embodiments of the teachings herein include a switching device for a DC voltage grid. The device may include: a first controllable semiconductor switch with a control contact and two load contacts; and a controller for the first switch using a control signal at the control contact. The controller is configured to: actuate the first switch using a control pulse that causes the electrical conductivity of the semiconductor switch to reduce for less than 1 ms; apply a current to a test circuit including the first switch; ascertain a first value representing the voltage or the change in voltage across the first switch as a result of the control pulse and the applied current; analyzing the first value; and generating a signal that represents the functionality of the first semiconductor switch.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: January 21, 2025
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Karsten Handt, Stefan Hänsel
  • Patent number: 12194875
    Abstract: This application provides a charging module and a charging system. The charging system includes a charging module. The charging module includes a direct current-to-direct current (DC/DC) charging component, a functional interface, an inverter, and a control and guide component. The functional interface includes a photovoltaic interface. The DC/DC charging component is configured to receive a first power exported by a photovoltaic module to charge an electric vehicle (EV). In this way, after receiving, through the photovoltaic interface, electrical energy converted from solar energy, the charging module does not need to cooperate with an on-board charger (OBC), but uses the DC/DC charging component to charge the EV with a direct current. The charging module provided in this application is not limited by a charging power of the OBC when charging the EV, thereby increasing an actual power for charging the EV and a charging speed.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: January 14, 2025
    Assignee: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Yanzhong Zhang, Xiaofeng Yao, Haibin Hu
  • Patent number: 12191848
    Abstract: A control circuit controls a switching element including a gate and a source corresponding to the gate. The control circuit includes an inductor, a circuit element, and a resistor. The inductor is connected between the gate and the source of the switching element. The circuit element is connected in series to the inductor between the gate and the source. The circuit element allows an electric current to flow therethrough in response to generation of electromotive force in the inductor. The resistor is connected in parallel to the inductor and the circuit element between the gate and the source.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: January 7, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Ryosuke Maeda, Yusuke Kinoshita, Hidetoshi Ishida
  • Patent number: 12191698
    Abstract: An electronic device may include a power management subsystem that soft-starts freshly charged batteries upon connection. The device may be configured to operate on power from a number of batteries less than the greatest number of batteries that may be concurrently connected. Because the soft-start reduces current inrush upon connection of a fresh battery, the device may continue operating as fresh batteries are connected and depleted batteries are disconnected.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: January 7, 2025
    Assignee: GOOGLE LLC
    Inventors: Chia Hang Yeh, Hsing-Sheng Lin
  • Patent number: 12191871
    Abstract: A TDC circuit configured to receive a reference clock (REF) signal and a signal derived from a LO; generate a plurality of digital values indicative of a measured phase difference between the signal derived from the LO and the REF signal, wherein each of the plurality of digital values are determined from a unique set of a plurality of sets of TDC measurement component quantization levels; generate a combined series of quantization levels based on a combination of the plurality of sets of TDC measurement component quantization levels; and determine a combined digital value from the combined series of quantization levels and at least one of the plurality of digital values to generate an output of the TDC circuit. The combined series of quantization levels may be generated by summing simultaneously occurring levels of each of the plurality of sets of TDC measurement component quantization levels together.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: January 7, 2025
    Assignee: Intel Corporation
    Inventors: Evgeny Shumaker, Elan Banin, Ofir Degani, Gil Horovitz
  • Patent number: 12179935
    Abstract: A method and power distribution system for operating in a low power consumption mode includes a primary power distribution node defining a primary distribution switch having an output and operable in a first conducting mode and a second non-conducting mode, and wherein operating in the second non-conducting mode includes a leakage current through the power distribution switch, at least one enabled electrical load downstream of the primary power distribution node, the at least one enabled electrical load connectable to the primary power distribution node by way of the primary distribution switch, and a primary power distribution node power source configured to supply power to the output of the primary distribution switch when the primary distribution switch is operating in the second non-conducting mode.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: December 31, 2024
    Assignee: E Aviation Systems Limited
    Inventor: David Alan Elliott
  • Patent number: 12184117
    Abstract: This application provides an uninterruptible power supply. An input end of the uninterruptible power supply is connected to a power supply by using a first on-off control module. A controller of the uninterruptible power supply is configured to: after receiving a first control signal sent by the first on-off control module, control a current in a circuit connecting the uninterruptible power supply and the first on-off control module to be zero. An output end of the uninterruptible power supply is connected to a load by using a second on-off control module. A controller of the uninterruptible power supply is configured to: after receiving a second control signal sent by the second on-off control module, control the uninterruptible power supply to be turned off.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: December 31, 2024
    Assignee: Huawei Digital Power Technologies Co., Ltd.
    Inventor: Chuntao Zhang
  • Patent number: 12174648
    Abstract: A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: December 24, 2024
    Assignee: M31 TECHNOLOGY CORPORATION
    Inventors: Ching-Hsiang Chang, Chih-Chieh Yao, Chun-Hsiang Lai