Abstract: A method in accordance with one embodiment of the invention can include detecting an interrupt request during execution of an instruction by a processor of an integrated circuit. Additionally, a clock signal frequency can be changed that is received by the processor. An interrupt service routine can be executed that corresponds to the interrupt request.

Abstract: A method for handling multiple system management interrupt (SMI) events in a multiprocessor system. The method comprises a first set of one or more processors in the multiprocessor system receiving a first SMI event. The first set of processors then enter an SMI handler for the first SMI event. The method further comprising determining that fewer than all of the active processors in the multiprocessor system are in the SMI handler for the first SMI event, and scheduling a second SMI event based upon the content of the first SMI event. The first set of processors each exit the SMI handler for the first SMI event without handling the first SMI event. Preferably, the method includes handling the second SMI event as a result of determining that all of the active processors in the multiprocessor system are in the SMI handler for the second SMI event.

Abstract: A first device is operable to communicate on an bus according to a first protocol. A bridge is also operable to communicate on the bus according to the first protocol. A second device is coupled to the bus via the bridge and operable to communicate according to a second protocol. The bridge has a memory for holding data received from the second device and is operable to translate from the second to the first protocol. The second device sends write data responsive to receiving a ready signal from the bridge, and includes memory for holding the write data that the second device has sent, but for which completion has not been signaled. The second device re-sends the write data from the memory responsive to receiving a non-completion signal via the bridge, and releases the memory for the data responsive to receiving a completion signal via the bridge.

Abstract: A processor surrogate (320/520) is adapted for use in a processing node (S1) of a multiprocessor data processing system (300/500) having a plurality of processing nodes (P0, S1) coupled together and to a plurality of input/output devices (330, 340, 350/530, 540, 550, 560) using corresponding communication links. The processor surrogate (320/520) includes a first port (372, 374/620, 622) comprising a first set of integrated circuit terminals adapted to be coupled to a first external communication link (370/590) for coupling (P0) of the plurality of processing nodes (310, 320/510, 520), a second port (382, 384/630, 632) comprising a second set of integrated circuit terminals adapted to be coupled to a second external communication link (380/592) for coupling to one (350/550) of the plurality of input/output devices (330, 340, 350/530, 540, 550, 560), and an interconnection circuit (390, 392/608, 612, 614) coupled between the first port (372, 374/620, 622) and the second port (382, 384/630, 632).

Abstract: A method of controlling a secure execution mode-capable processor includes allowing a plurality of interrupts to interrupt the secure execution mode-capable processor when the secure execution mode-capable processor is operating in a non-secure execution mode. The method also includes disabling the plurality of interrupts from interrupting the secure execution mode-capable processor when the secure execution mode-capable processor is operating in a secure execution mode.

Abstract: A resource allocation arbitration system. The system includes a plurality of storage devices, a plurality of indicators, and a plurality of mask bits. Each storage device stores requests for resources. Each indicator enables indication of a condition in which the request stored in each storage device is almost empty. Furthermore, the mask bits enable preemption of one request by another request.

Abstract: Disclosed is an apparatus and method for flexible controlling endpoint memory within an USB device. In one embodiment, the method includes a USB device receiving a first token packet from a USB host, wherein the first token packet includes a first endpoint number. The first endpoint number is stored into a first tag in memory corresponding to a first data buffer in the USB device. The USB device then receives a data packet from the USB host, wherein the data packet comprises endpoint data. The; endpoint data of the data packet is stored into the first data buffer.

Abstract: A method for transceiving non-USB peripheral device by an adapter and the adapter providing adaptation to an USB interface for the non-USB peripheral device, is disclosed. The adapter can read a capability report from the peripheral device and then converts the capability report to an USB-related report for facilitating accessing of the peripheral device. The adapter utilizes control commands and parameter set pre-defined by the adapter and the peripheral device to successfully access the peripheral device. The peripheral device has vendor identification (VID) and product identification (PID) and the controller transceives or detects the peripheral device with reference to the information of VID and PID.

Abstract: A communication interface responds to a communication protocol for interfacing a controller and any of a plurality of discrete I/O devices. Each discrete I/O device has a different configuration. The interface has a plurality of modes of operation to accommodate the discrete I/O devices. In a first mode of operation, the interface accommodates a first discrete I/O device wherein a plurality of input pins input signals from a particular discrete I/O and a plurality of output pins output signals to the particular discrete I/O device. In a second mode of operation, the interface accommodates a second discrete I/O device wherein the input pins form a bidirectional input/output port and the output pins form a control and address line for controlling the second discrete I/O device and other discrete I/O devices.

Abstract: A peripheral device for use in a system including a storage unit coupled to a local bus. The peripheral device has a shared bus interface provided for interfacing with the storage unit and the local bus. The peripheral device also includes core logic coupled to the shared bus interface. When the core logic receives a read/write command with respect to the storage unit through the local bus, it causes the local bus to enter at least a wait state and performs a corresponding data transfer between the peripheral device and the storage unit through the shared bus interface during the wait state. In particular, the peripheral device shares the shared bus interface with the storage unit so as to transfer data.

Abstract: The invention relates to a virtual processor through USB (VPTU), which is installed in a peripheral with USB interface specifications and comprises an I/O instruction decoding unit for decoding or compiling received and compiled instructions of USB packets for parsing the instructions and converting the same into instructions identifiable by an application chipset of the peripheral or a CPU of a computer in order to eliminate microprocessors and memory devices of a conventional peripheral complied with the USB interface specifications and perform operations involved in the transmission or receiving of the USB packets and storing USB interface programs and intermediate data created in the operations.