Patents Examined by Ryan Stiglic
  • Patent number: 9213380
    Abstract: Mapping computers and ports of power distribution units in a data center, the data center including a plurality of computers and a data center management server, each computer in the data center connected for power to one of a plurality of power distribution unit (‘PDU’) ports of a PDU, each PDU connected through the communications module and a data communications network to the data center management server, including generating, by a power modulating module of a computer, a power consumption signal in the PDU, the power consumption signal encoding a unique identification of the computer; demodulating, by the PDU, the power consumption signal, including retrieving from the signal the unique identification of the computer; and reporting, by the PDU to the data center management server, an association of the unique identification of the computer and a PDU port.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: December 15, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Justin P. Bandholz, William J. Piazza, Philip L. Weinstein
  • Patent number: 9176770
    Abstract: Generally, this disclosure describes systems (and methods) for moderating interrupts in a virtualization environment. An overflow interrupt interval is defined. The overflow interrupt interval is used for triggering activation of an inactive guest so that the guest may respond to a critical event. The guest, including a network application, may be active for a first time interval and inactive for a second time interval. A latency interrupt interval may be defined. The latency interrupt interval is configured for interrupt moderation when the network application associated with a packet flow is active, i.e., when the guest including the network application is active on a processor. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: November 3, 2015
    Assignee: Intel Corporation
    Inventors: YaoZu Dong, Yunhong Jiang, Kun Tian
  • Patent number: 9164935
    Abstract: Provided are a computer program product, system, and method for determining when to throttle interrupts to limit interrupt processing to an interrupt processing time. Upon receiving interrupts from the hardware device, a determination is made as to whether a number of received interrupts exceeds an interrupt threshold during a interrupt tracking time period. If so, an interrupt throttling state is set to a first value indicating to only process interrupts during an interrupt processing time period. Interrupts from the hardware device are processed during the interrupt time period when the interrupt throttling state is set to the first value. Interrupts received from the hardware are masked during a processing of a scan loop of operations while the interrupt throttling has the first value and the interrupt processing time period has expired, wherein the masked interrupts are not processed while processing the scan loop of operations.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: October 20, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven E. Klein, Timothy J. Van Patten
  • Patent number: 9146611
    Abstract: To conserve power in a controlling device having a processing device in communication with an input element and a transmitting device the processing device is caused to be placed into a low-power state for at least a portion of a transmission inactive interval intermediate the transmission of at least a pair of command frames. The command frames are caused to be transmitted by the transmitting device in response to an activation of the input element sensed via the processing device to thereby command a functional operation of an intended target device.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: September 29, 2015
    Assignee: Universal Electronics Inc.
    Inventors: Arsham Hatambeiki, Christopher Lee Sommerville, Weidong William Wang
  • Patent number: 9137038
    Abstract: The node communication controller (NCC) suitable for use in a line-replaceable unit (LRU) of a modular avionics system may include one or more embedded processors configured to host one or more functions associated with at least one avionics module of an avionics system, an input/output (I/O) controller, and one or more I/O ports, wherein the I/O controller is configured to route data between the one or more embedded processors and the at least one avionics module via the one or more I/O ports and a network communication bus, wherein the I/O controller is further configured to route data between a host processor of the LRU and an additional avionics module via the one or more I/O ports and the network communication bus.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: September 15, 2015
    Assignee: Rockwell Collins, Inc.
    Inventors: Daniel E. Mazuk, David A. Miller, Clifford R. Klein, Savio N. Chau, Eric N. Anderson
  • Patent number: 9135193
    Abstract: In one example in accordance with aspects of the present disclosure, an expander is provided. The expander comprises a workload scheduling module to cause the expander to enter a first mode of operation where the expander processes interrupts, and further to enter a second mode of operation where the expander processes interrupts for up to a predetermined time period before responding to at least one of Serial Management Protocol (SMP) commands and Serial SCSI Protocol (SSP) commands with a retry message.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: September 15, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael G. Myrah, Balaji Natrajan, Rodrigo Stoll Martins Machado
  • Patent number: 9137005
    Abstract: Systems and methods presented herein provide for the management of link rates for connecting targets devices (e.g., storage devices) to initiators (e.g., host systems). In one embodiment, an expander includes a plurality of PHYs including a PHY having a first link rate and a PHY having a second link rate that is different than the first link rate. The expander also includes a link manager communicatively coupled to the PHYs and operable to process a connection request from an initiator for the first link rate, extract a timer from the connection request, and determine whether the first link rate is available. The link manager is also operable to start the timer when the link manager determines that the first link rate is unavailable and issue a response to the initiator to inform the initiator that the timer has started and that connection at the first link rate is delayed.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: September 15, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte Ltd
    Inventors: Jeffrey C. Weide, Reid A. Kaufmann, Charles D. Henry
  • Patent number: 9135210
    Abstract: In one embodiment of the present invention, processor 1000 comprising a plurality of processor cores for processing an instruction-execution sequence is provided. Signal path 140 that is able to communicate an inter-core interrupt signal fint is connected to at least two processor cores 100A and 100B. Each core of the at least two cores has an inter-core interrupt count setting register (ICSR) 110 and a FIFO counter 120. Inter-core interrupt synchronization function, inter-core interrupt generation function, and FIFO counter updating function are implemented to the every core. In embodiments of the present invention, a core and a method therefor are also provided.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: September 15, 2015
    Assignee: TOPS SYSTEMS CORPORATION
    Inventors: Yukoh Matsumoto, Hiroyuki Uchida
  • Patent number: 9130824
    Abstract: Certain aspects of the present disclosure are directed to a baseboard management controller (BMC). The BMC includes a processor and a memory having firmware. The firmware includes a master management instance and a plurality of assisting management instances. When the firmware is executed at the processor, the master management instance is configured to manage a chassis of a computer system, and each of the assisting management instances is configured to manage at least one health or performance related aspect a respective different computer node of a plurality of computer nodes of the computer system.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: September 8, 2015
    Assignee: AMERICAN MEGATRENDS, INC.
    Inventors: Anurag Bhatia, Winston Thangapandian
  • Patent number: 9128719
    Abstract: A controlling circuit supporting a power saving mechanism includes: a transmitting interface arranged to perform a signal transmission with a specific controlling circuit; and a setting unit coupled to the transmitting interface. The setting unit is arranged to control the specific controlling circuit to operate in the power saving mechanism.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: September 8, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventors: Liang-Wei Huang, Ta-Chin Tseng, Chi-Shun Weng, Shieh-Hsing Kuo
  • Patent number: 9128900
    Abstract: In a method for managing redundant arrays of independent disks (RAID) cards and a server for executing the method, the server calculates a theoretical percentage of a load of each RAID card according to a number of the RAID cards, and loads an actual percentage of the load of each RAID card through a multi input output (MIO) interface, and detects peripheral component interconnect-express (PCI-E) bandwidth of each RAID card. When the load of each RAID card is unbalanced or the PCI-E bandwidth of the RAID card is saturated, the server transfers the load from a RAID card having a greater actual percentage of the load into a RAID card having a less actual percentage of the load, and transfers the load from a RAID card whose PCI-E bandwidth is saturated into a RAID card whose PCI-E bandwidth is unsaturated according to differential signals through the MIO interface.
    Type: Grant
    Filed: April 6, 2013
    Date of Patent: September 8, 2015
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Chih-Huang Wu
  • Patent number: 9117033
    Abstract: A method, device, and system for packet transmission on the PCIE bus according to the embodiments of the present invention, a SCSI protocol packet is encapsulated to obtain an encapsulated SCSI protocol packet, and the encapsulated SCSI protocol packet is carried in a PCIE data packet, and then the PCIE data packet carrying the encapsulated SCSI protocol packet is transmitted to the receiver device through the PCIE bus. Thereby, transmission of SCSI protocol packets is implemented on the PCIE bus, and any devices interconnected through the PCIE bus can operate each other through SCSI protocol packets with a high data transmission bandwidth and high processing speed, without requiring a specific physical device or adapter to perform protocol conversion.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 25, 2015
    Assignee: Huawei Digital Technologies (Cheng Du) Co. Limited.
    Inventors: Zhihong Gao, Ke Li
  • Patent number: 9116881
    Abstract: The present disclosure relates to a routing switch apparatus, a network switch system, and a routing switch method. The routing switch apparatus includes one or more direct memory access modules and at least two protocol conversion interfaces. The direct memory access module is configured to generate a continuous access request of a cross network node, and control data transmission in the at least two protocol conversion interfaces; each protocol conversion interface is configured to convert a communication protocol of data transmitted inside and outside the routing switch apparatus and connect the routing switch module and an external network node. The routing switch apparatus may be introduced to replace a network switch, so that cross-node memory access and IO space access can be performed directly rather than through a proxy, thereby reducing delay of the cross-node memory access and IO space access and improving overall performance of a system.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 25, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yunhai Liu, Junfeng Diao
  • Patent number: 9116695
    Abstract: A non-transitory computer readable medium stores instructions that, when executed, cause a data processing apparatus, which includes a first input/output section and which is driven by a battery, to: judge whether the first input/output section is set as the input/output section; judge whether the remaining battery level of the battery is not less than a first reference remaining level; judge whether the data processing apparatus includes a second input/output section requiring a power consumption lower than that of the first input/output section; and switch or output a notification to switch the input/output section from the first input/output section to the second input/output section, in a case that the first input/output section is set as the input/output section; that the remaining battery level is less than the first reference remaining level; and that the data processing apparatus includes the second input/output section.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: August 25, 2015
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventor: Ryo Yasui
  • Patent number: 9117037
    Abstract: An interface apparatus, a cascading system thereof, and a cascading method thereof are provided. The cascading system includes a host, a first-type interface apparatus, and a second-type interface apparatus which are serially connected. The host provides data transmission of a first and a second channel by a first controller through a first interface port. In the first-type interface apparatus, data of the first channel is transmitted to a second controller through a second interface port and then to a third interface port, and data of the second channel is directly transmitted to the third interface port through the second interface port. In the second-type interface apparatus, the data of the second channel are transmitted to a third controller through a forth interface port and then to the fifth interface port, and the data of the first channel is directly transmitted to the fifth interface port through the forth interface port.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: August 25, 2015
    Assignee: Acer Incorporated
    Inventor: Sip Kim Yeung
  • Patent number: 9104822
    Abstract: A signal transmission method for a USB interface and an apparatus thereof are provided. The method includes: receiving a first USB signal sent from a sending terminal, processing the first USB signal into a USB-like signal, and transmitting the USB-like signal via a networking cable; receiving the USB-like signal, processing the USB-like signal into a second USB signal, and sending the second USB signal to a receiving terminal. According to the embodiments of the present invention, the first USB signal is processed into a USB-like signal which is similar to the USB signal, the USB-like signal is transmitted via a networking cable, and the USB-like signal is processed into a second USB signal. The transmission process does not require converting the USB signal into a networking-cable signal which is to be transmitted via a networking cable, thereby avoiding conversion between protocols, and simplifying the entire transmission process.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: August 11, 2015
    Assignee: LONTIUM SEMICONDUCTOR CORPORATION
    Inventors: Jiaxi Fu, Hui Bian, Shengquan Hu, Lianliang Tai, Feng Chen, Chaoqun Chu, Qingwei Liu, Guangren Li
  • Patent number: 9104816
    Abstract: A memory card is disclosed including first and second host interfaces facilitating the communication of data between the memory card and a host using, respectively, first and second protocols, wherein the first protocol defines low-speed operations and the second protocol defines high-speed operations for the memory card. The second host interface is only enabled in response to an indication by the host device of a high-speed memory card operation.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: August 11, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kee-hoon Lee
  • Patent number: 9104639
    Abstract: Methods, systems, and devices for distributed computing are provided. Clusters of nodes are provided, each node have a communication link to a primary I/O switch as well as to two other nodes, thereby providing redundant alternative communication paths between different components of the system. Primary and redundant I/O switching modules may provide further redundancy for high availability and high reliability applications, such as applications that may be subjected to the environment as would be found in space, including radiation effects. Nodes in a cluster may provide data storage, processing, and/or input/output functions, as well as one or more alternate communications paths between system components. Multiple clusters of nodes may be coupled together to provide enhanced performance and/or reliability.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: August 11, 2015
    Assignee: SEAKR Engineering, Inc.
    Inventors: Brett Koritnik, Kirk Sprague
  • Patent number: 9094317
    Abstract: A first processor has a processor port for peer-to-peer processor communications. A switch provides for switching communications from a path between said first processor and a second processor to a path between said first processor and a third processor (and vice-versa).
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: July 28, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Martin Goldstein, Kamran H. Casim, Loren M. Koehler
  • Patent number: 9081912
    Abstract: The present invention discloses a method and an apparatus for node hot-swapping, which simplify the node hot-adding procedure, and improve the operation efficiency of the hot-adding procedure. The present invention includes: obtaining, by a server from a baseboard management controller BMC of a node device to be added, static hardware information of the node device to be added, and storing it into a storage device of the server, where the static hardware information is obtained through an out-band channel by the BMC of the node device to be added; receiving, by the server, a node hot-adding command sent by a user, where the hot-adding command carries identifier information of the node device to be added; obtaining the static hardware information of the node device to be added corresponding to the identifier information from the storage device; and adding, according to the static hardware information, the node device to be added.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: July 14, 2015
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yixiang Liao, Dengben Wu, Yu Zhang