Patents Examined by S. Crane
  • Patent number: 4757363
    Abstract: An input resistor-diode protection circuit having an input resistor formed by a high impurity region within a deeper low impurity region, both a first conductivity type and input diode formed by the junction of the low impurity resistor region and the substrate along a substantial portion and a high impurity region overlapping the low impurity region at the output end of the resistor-diode circuit, both of a second conductivity type. A bipolar transistor connected to the output of the resistor in parallel to the diode also provides protection. A pair of concentric guard rings of first and second conductivity type laterally encompasses the input protection circuit.
    Type: Grant
    Filed: October 3, 1986
    Date of Patent: July 12, 1988
    Assignee: Harris Corporation
    Inventors: Michael A. Bohm, W. Ronald Young
  • Patent number: 4670767
    Abstract: The bipolar transistor comprises an emitter of a first semiconductor, a base of a second semiconductor and a collector of a third semiconductor, the first semiconductor having edges of conduction and valence bands positioned outside the energy band gap of the second semiconductor, and the third semiconductor having an edge of conduction band for majority carriers positioned inside the energy band gap of the second semiconductor and an edge of valence band for majority carriers positioned outside the energy band gap of the second semiconductor.
    Type: Grant
    Filed: January 30, 1985
    Date of Patent: June 2, 1987
    Assignee: NEC Corporation
    Inventor: Kuniichi Ohta
  • Patent number: 4608589
    Abstract: A self-aligned metal integrated circuit structure is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces.
    Type: Grant
    Filed: July 11, 1983
    Date of Patent: August 26, 1986
    Assignee: International Business Machines Corporation
    Inventors: George R. Goth, Ingrid E. Magdo, Shashi D. Malaviya
  • Patent number: 4591889
    Abstract: Semiconductor devices having submonolayer superlattices are described. These devices may have periodic compositional variations in a direction parallel to the substrate surface as well as in the perpendicular direction. Such superlattices are useful in numerous types of devices including lasers, transistors, etc.
    Type: Grant
    Filed: September 14, 1984
    Date of Patent: May 27, 1986
    Assignee: AT&T Bell Laboratories
    Inventors: Arthur C. Gossard, Pierre M. Petroff
  • Patent number: 4590505
    Abstract: A three dimensional optical image receiver having sensor stages with a programmable gain capability. Operation of the receiver occurs entirely in the charge domain upon the charge initially generated by the optical signal.
    Type: Grant
    Filed: January 10, 1984
    Date of Patent: May 20, 1986
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Nathan Bluzer