Abstract: A semiconductor integrated circuit is so designed that it is possible to form any one of the three different kinds of circuit configuration, that is, an inverter circuit, a Schmitt circuit and a common-mode circuit, as desired, by employing circuit elements prepared in advance and by changing wiring. Also disclosed is a semiconductor integrated circuit having these circuit configurations. The output stage of any one of the three kinds of circuit is constituted by a bipolar transistor, and the other portions are constituted by MOS field-effect transistors.

Abstract: The lower output pulldown tristate circuit for a TTL tristate output buffer circuit includes the enable signal invertor buffer having an OE signal input and an OE signal output providing output enable OE signals, and a Miller killer transistor element having collector and emitter nodes coupled between the base node of the TTL tristate output pulldown transistor and the low potential power rail. The base node of an emitter follower transistor element is coupled to the OE signal input and the emitter node provides a DC Miller killer DCMK signal output in phase with the OE signal input. A voltage divider couples the DCMK signal output to the base node of the Miller killer transistor element for discharging the base of the output pulldown transistor in response ot a high potential DCMK signal during the high impedance tristate at the output. The DC Miller killer circuit is applied in a high speed TTL tristate output and multi-bit line driver.

Abstract: A multi-function circuit including an oscillator, a pulse generator and an integrator which share a common timing capacitor. The pulse generator is run by double ended charging of the timing capacitor. The integrator shares the threshold setting circuitry of the oscillator and in turn the pulse generator shares and makes use of the threshold setting circuitry of both the integrator and the oscillator. During operation of the pulse generator, positive feedback through the capacitor aids in providing a rapid and complete discharging of the timing capacitor 16 below the lower threshold of the oscillator. A selector input selects between the oscillator and pulse generator and the integrator provides a predetermined time delay in which the selection is verified.

Abstract: A semiconductor integrated circuit device comprising a logic circuit which is constituted by using tri-state IIL gates. The tri-state IIL gates are particularly arranged to have first and second inputs. If the second input has a first level, the circuit will operate as a normal IIL circuit to provide high and low outputs in response to the first input. However, if the second input has a second level, the circuit will provide a floating output regardless of the first input. The transistors of the IIL circuit can be formed in an island in the substrate, with the potential of the island serving as the second input. In a preferred arrangement, the first level of the second input can be obtained by grounding the island while the second level is obtained by disconnecting the island from ground. These tri-state IIL gates are particularly advantageous to form a transfer gate for an IIL memory similar to the transfer gates used for MOS memories. They can also be used for forming various other logic gate arrangements.

Abstract: A liquid crystal light valve projector is disclosed which includes source illumination appratus which images an illumination aperture at the liquid crystal light valves, and further includes light valve imaging apparatus for relaying the light valve images to a wide angle projection lens having a short back focal length. The disclosed liquid crystal light valve projector utilizes air separated dichroic color separator for providing primary color illumination to the light valves.

Abstract: Described is an antisaturation circuit for an integrated PNP transistor characterized by a comparator circuit comprising two transistors and a current generator whose output current corresponds to a pre-established function, e.g., an exponential function, of the emitter current of said transistor. The changing of state of the comparator circuit, as determined by said pre-established function of said current generator, is determined by the drop of the V.sub.CE voltage of the transistor below a preset minimum value, with a portion of the conduction current of one of the two transistors of the comparator circuit utilized for increasing the forced .beta. of the transistor. This limits the degree of its saturation, as well as the leakage current toward the substrate.

Abstract: An output circuit comprises an output transistor circuit for applying an output signal to a transmission line connected to an output terminal, a circuit for driving the output transistor circuit in response to an input signal applied to an input terminal, and a control circuit by which the signal amplitude of a first wave applicable to the transmission line with a load connected to the output terminal through the transmission line is rendered approximately one half of the output signal amplitude with a load directly connected to the output terminal. The control circuit includes a monitoring transistor within the same chip as the output transistor circuit, a selected one of the output resistance and input signal of the output transistor circuit being controlled in accordance with the magnitude of the drain current of the monitoring transistor to adjust the amplitude of the signal applied to the transmission line.

Abstract: A light source, which has a time varying chromatic output, back lights or front lights a plurality of liquid crystal displays disposed in a desired arrangement. Two different colors can be produced at two different times by using a fluorescent light as the light source. The fluorescent light is a sealed tube having a high vacuum with an insert gas therein for energization of the gas and a low pressure mercury vapor. The tube has a coating on the inner surface of the tube of at least one phosphor. Energization of the inert gas causes the low pressure mercury vapor to arc to produce light of a first color during a first time period with the light of the second color being produced solely from the phosphor coating upon the gas being deenergized during the second time period. Each of the liquid crystal displays can be activated during the first time period, the second time period, both time periods, or remain inactivated during both time periods.

Abstract: A semiconductor integrated device and a method for manufacturing the same, the device comprising an internal semiconductor integrated circuit which includes N-MOS transistors, and a P-MOS output transistor having a source connected to a voltage power supply. The drain of the P-MOS transistor is connected to an output terminal and the output terminal is operatively connected to a device driven by the P-MOS transistor.

Abstract: A clock detector has a D flip-flop having a D terminal, a reset terminal and a clock terminal, a first saw-tooth wave signal generator having a first time constant for supplying to the D terminal a first logic signal resulting from a first saw-tooth wave signal, and a second saw-tooth wave signal generator having a second time constant which is larger than the first time constant for supplying to the reset terminal a second logic signal resulting from a second saw-tooth wave signal. A first clock pulse is supplied to the first and second saw-tooth wave signal generators, and a second clock pulse is applied to the clock terminal of the D flip-flop. When a reciprocal of a frequency of the first and second clock pulses falls within the first and second time constants, a normal clock pulse is detected.

Abstract: An adjustable frequency ON/OFF delay circuit 2 is provided by ON and OFF delay counters 6 and 14 and respective adjustable frequency oscillators 4 and 20. The ON delay counter 6 is enabled by an input ON signal and clocked by its oscillator 4 to a given count for outputting a delayed output ON signal. This counter 6 is disabled by an input OFF signal and outputs the OFF signal without delay. The second counter 14 responds to the first counter 6 for outputting the delayed output ON signal without further delay, and for delaying the output OFF signal. Circuit 2 is ideal for proximity switch applications, particularly photoelectric type proximity switches, for providing a delayed output signal following a given sensed condition.

Abstract: The ladder network of a recirculation of remainder analog to digital converter has a voltage source that is regulated by a transistor and Zener diode together with feedback circuitry responsive to the regulated output voltage. Current through the circuit is controlled by feedback to establish equal and opposite temperature coefficients in the transistor and Zener diode of the regulator. The temperature stabilized voltage regulator produced thereby eliminates any requirement for trimmer potentiometers.

Abstract: An address decoder architecture capable of having a precharge signal for the word line coincident with the enabling of the decoder section to reduce the operating cycle. The word line latch is separate and distinct from the word line driver such that disablement of the word line driver during readdressing of the enabled decoder will not effect the portion of the cycle that the word line maintains its logic state.

Abstract: An input circuit having a plurality of channels, each channel includes a conductor line, first and second transistors inserted in series into the conductor line and a third transistor.When a channel is not selected, the first and second transistors are turned off and the third transistor is turned on to clamp the conductor line at a predetermined constant voltage. When a channel is selected, the third transistor is turned off and first and second transistors are turned on to transfer the corresponding information input therethrough.

Abstract: A positive voltage supply is connected to a circuit having a single capacitor and depletion-type field-effect transistor to create a reliable timer. The capacitor is initially charged upon the opening of a control switch without creating a timed output across the drain-source terminals of the field-effect transistor. The closing of the switch reverses the bias of the single capacitor to the gate-source connections of the field-effect transistor to thereby create a fixed and reliable timed interval.

Abstract: Bipolar inputs are afforded by the plus inputs of first and second differential input amplifiers. A first gain determining resister is connected between the minus inputs of the differential amplifiers. First and second diodes are connected between the respective minus inputs and the respective outputs of the differential amplifiers. First and second FETs have their gates connected to the outputs of the amplifiers, while their respective source and drain circuits are connected between the respective minus inputs and an output lead extending to a load resister. The output current through the load resister is proportional to the absolute value of the input voltage difference between the bipolar input terminals. A third differential amplifier has its plus input terminal connected to the load resister. A second gain determining resister is connected between the minus input of the third differential amplifier and a voltage source. A third FET has its gate connected to the output of the third amplifier.

Abstract: An optically coupled solid state relay circuit is disclosed. A light emitting diode input circuit is utilized to trigger a photosensitive transistor. A trim resistor in the base of the photosensitive transistor is utilized to adjust the sensitivity of the circuit. The photosensitive transistor is utilized, in conjunction with other circuitry, to control a silicon controlled rectifier which provides gate drive to a triac. Voltage limiting circuitry is provided to insure that the solid state relay will switch only during those periods within a selected range of the zero crossing of the line voltage and half of the bridge circuit which provides single polarity operating voltages is comprised of fast recovery diodes to improve the circuit's ability to withstand rapid polarity reversals.