Patents Examined by S. Jaser
  • Patent number: 4575796
    Abstract: An information processing unit designed for operating on N-bit bytes is capable of handling 2N-bit bytes in parallel. Control multiplexers selectively switch the connections between read and write buffers and a pair of bus lines. When 2N-bit processing is needed the multiplexers alter the connection between the bus lines and the buffers. The altered connection plus other normal buffer to bus line connections permit an increase in the data length that can be read or written simultaneously.
    Type: Grant
    Filed: February 13, 1985
    Date of Patent: March 11, 1986
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Ikutaro Wako