Patents Examined by Sakhr A Aldaylam
  • Patent number: 11435949
    Abstract: An information processing apparatus includes a storage unit configured to store data, a write control unit configured to instruct the storage unit to write data, a calculation unit configured to calculate, for each of a plurality of writes of data to the storage unit, a data size estimated to be actually written to the storage unit, based on a write data size specified by the write control unit, and a notification unit configured to issue a notification based on a total of the data sizes calculated by the calculation unit.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: September 6, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yoshikazu Sato
  • Patent number: 11409666
    Abstract: Techniques for processing I/O operations may include: issuing, by a process of an application on a host, an I/O operation; determining, by a driver on the host, that the I/O operation is a read operation directed to a logical device used as a log to log writes performed by the application, wherein the read operation reads first data stored at one or more logical addresses of the logical device; storing, by the driver, an I/O flag in the I/O operation, wherein the I/O flag has a first flag value denoting an expected read frequency associated with the read operation; sending the I/O operation from the host to the data storage system; and performing first processing of the I/O operation on the data storage system, wherein said first processing includes using the first flag value in connection with caching the first data in a cache of the data storage system.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: August 9, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Gabriel Benhanokh, Sanjib Mallick, Arieh Don
  • Patent number: 11366763
    Abstract: A controller, a memory system and an operating method thereof are disclosed. The controller controls a nonvolatile memory device and the nonvolatile memory includes a first memory module configured to store a plurality of pieces of map data read from the nonvolatile memory device; and a second memory module configured to cache map data having locality among map data received from the first memory module.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Do Hun Kim
  • Patent number: 11360885
    Abstract: In an embodiment, a system includes a plurality of memory components that each include a plurality of management groups. Each management group includes a plurality of sub-groups. The system also includes a processing device that is operatively coupled with the plurality of memory components to perform wear-leveling operations that include maintaining a sub-group-level delta write count (DWC) for each of the sub-groups of each of the management groups of a memory component in the plurality of memory components. The wear-leveling operations also include determining, in connection with a write operation to a first sub-group of a first management group of the memory component, that a sub-group-level DWC for the first sub-group equals a management-group-move threshold, and responsively triggering a management-group-move operation from the first management group to a second management group of the memory component.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Paul Stonelake, Ning Chen, Fangfang Zhu, Alex Tang
  • Patent number: 11327904
    Abstract: System, methods, and other embodiments described herein relate to improving security of protected values in a memory. In one embodiment, a method includes, in response to receiving a write request indicating at least an item and a write value to write into the memory, determining whether a protected items list (PIL) indicates that the item is protected. The method includes replacing the write value of the write request with a protected value from the PIL that corresponds with the item when the item is listed in the PIL as being protected. The method further includes executing the write request to the memory.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: May 10, 2022
    Assignees: Denso International America, Inc., Denso Corporation
    Inventor: David M. West
  • Patent number: 11327903
    Abstract: An apparatus has memory access circuitry to perform a tag-guarded memory access operation in response to a target address. The tag-guarded memory access operation comprises: comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address, and generating an indication of whether a match is detected between the guard tag and the address tag. An instruction decoder decodes a multiple guard tag setting instruction to control the memory access circuitry to trigger memory accesses to update the guard tags associated with at least two consecutive blocks of one or more memory locations.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 10, 2022
    Assignee: Arm Limited
    Inventor: Graeme Peter Barnes
  • Patent number: 11188264
    Abstract: A memory system includes a nonvolatile (NV) memory device with asymmetry between intrinsic read operation delay and intrinsic write operation delay. The system can select to perform memory access operations with the NV memory device with the asymmetry, in which case write operations have a lower delay than read operations. The system can alternatively select to perform memory access operations with the NV memory device where a configured write operation delay that matches the read operation delay.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Shekoufeh Qawami, Philip Hillier, Benjamin Graniello, Rajesh Sundaram
  • Patent number: 11176057
    Abstract: An indication is received from a host application of a first minimum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks, wherein the first minimum retention time is not indicated for a second plurality of tracks. Based on the first minimum retention time, a second minimum retention time is set for the first plurality of tracks for the first type of memory and a third minimum retention time is set for the first plurality of tracks for the second type of memory. A track of the first plurality of tracks is demoted from the first type of memory, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the first type of memory and the track has been in the first type of memory for a time that exceeds the second minimum retention time.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Beth Ann Peterson, Kyler A. Anderson
  • Patent number: 11169927
    Abstract: A distributed cache is managed. In some embodiments, only a subset of a plurality of processing nodes may be designated as cache managers that manage the cache access history of a logical area, including having an exclusive right to control the eviction of data from cache objects of the logical area. In such embodiments, all of the processing nodes may collect cache access information, and communicate the cache access information to the cache managers. Some of the processing nodes that are not cache managers may collect cache access information from a plurality of the other non-cache managers. Each such processing node may combine this communicated cache access information with the cache access information of the processing node itself, sort the combined information per cache manager, and send the resulting sorted cache access information to the respective cache managers. The processing nodes may be arranged in a cache management hierarchy.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: November 9, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Gabriel Benhanokh, Arieh Don
  • Patent number: 11144454
    Abstract: Metadata in volatile memory is selectively compressed and destaged to non-volatile storage in the event of an emergency shutdown due to loss of like power. Compression offload hardware that is normally used for data compression is used to compress the metadata, e.g. at line speed. The compressed metadata and any uncompressed metadata that was not selected for compression may be destaged to vault drives along with compressed and uncompressed data that is in the volatile memory. Compression during vaulting may decrease power consumption when operating under standby battery power.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: October 12, 2021
    Assignee: Dell Products L.P.
    Inventors: James Guyer, Jason Duquette
  • Patent number: 11113159
    Abstract: An embodiment of a memory apparatus may include a logger to log memory access data in persistent storage media, a log indexer communicatively coupled to the logger to index the memory access log data in an index table in a system memory, and a key compressor communicatively coupled to the log indexer to compress an index key for the index table. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Zhiyuan Zhang, Xiangbin Wu, Xinxin Zhang, Qianying Zhu, Haitao Ji, Yingzhe Shen
  • Patent number: 11106380
    Abstract: Data storage of workloads is migrated from a local computing environment to a cloud computing environment. The workloads are first executed in a runtime environment that have been deployed within a first virtual machine running in the local computing environment, according to a blueprint that defines a data storage path for the workloads. The data storage of the workloads is migrated by copying contents of a first file, which corresponds to a virtual disk of the first virtual machine, to a second file, modifying the blueprint to change the data storage path to a path that specifies a file path to the second file, and deploying a runtime environment within a second virtual machine running in the cloud computing environment, according to the modified blueprint. After transitioning the data storage of the workloads in this manner, the workloads are executed in the runtime environment deployed within the second virtual machine.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: August 31, 2021
    Assignee: VMware, Inc.
    Inventors: Junfei Wu, Zongmin Li, Qi Kang, Haisheng Kang, Jinhua Chen