Abstract: A method of fabrication wherein a nitride layer is spaced from a conductive substrate by an insulating layer and etching removes at least portions of an insulating layer to leave a nitride membrane spaced from the substrate. The surface of the conductive layer where the insulating layer is removed is chemically roughened and the etchant is removed by freeze-drying and sublimation to eliminate sticking of the nitride layer to the substrate surface during fabrication.

Abstract: In a silicon wafer having a CVD film formed on one main face and having the other main face mirror-polished, the components and/or composition of the CVD film change in the thicknesswise direction of the film. This makes it possible to provide a silicon wafer having a thin film provided on the back surface, which thin film has excellent and persistent gettering capability that can remove a greater variety of types of elements and can prevent autodoping.

Abstract: A method for forming a barrier layer inside a contact in a semiconductor wafer is disclosed herein. The forgoing semiconductor wafer includes a dielectric layer on a silicon contained layer. A portion of the silicon contained layer is exposed by the contact. The method mentioned above includes the following steps.First, form a conductive layer on the topography of the semiconductor wafer by a method other than CVD to increase the ohmic contact to the exposed silicon contained layer. Thus a first portion of the conductive layer is formed on the dielectric layer, and a second portion of the conductive layer is formed on the exposed silicon contained layer. Next, remove the first portion of the conductive layer to expose the dielectric layer. Finally, use a chemical vapor deposition (CVD) method to form the barrier layer on the dielectric layer and the first portion of the conductive layer to prevent said silicon contained layer from exposure.

Abstract: A liquid precursor is provided for the formation of metal oxide films comprising a mixture of two ro more types of beta-diketonate ligands bound to one or more metals. For example, a liquid mixture was formed of the mixed aluminum beta-diketonates derived from two or more of the ligands 2,6-dimethyl-3,5-heptanedione; 2,7-dimethyl-3,5-heptanedione; 2,6-dimethyl-3,5-octanedione; 2,2,6-trimethyl-3,5-heptanedione; 2,8-dimethyl-4,6-nonanedione; 2,7-dimethyl-4,6-nonanedione; 2,2,7-trimethyl-3,5-octanedione; and 2,2,6-trimethyl-3,5-octanedione. Films of metal oxides are deposited from vaporized precursor mixtures of metal beta-diketonates and, optionally, oxygen or other sources of oxygen. This process may be used to deposit high-purity, transparent metal oxide films on a substrate. The liquid mixtures may also be used for spray coating, spin coating and sol-gel deposition of materials.

Abstract: A method of manufacturing a transistor capable of obtaining a BICMOS while making the difference in the number of manufacturing processes from a CMOS smaller, includes the steps of: separating an element region in a semiconductor substrate; forming a emitter opening for deciding upon an emitter layer in an insulating film on the semiconductor substrate, forming a polysilicon film on the insulating film and in the emitter opening; implanting selectively impurity ions into the semiconductor substrate through the polysilicon film and the insulating film to form: a collector layer and a base layer; and performing heat treatment for activating impurities in the base layer and the collector layer and diffusing impurities into the semiconductor substrate from the polysilicon film to form an emitter diffused layer.

Abstract: The method of polishing metal layers on wafers comprises the steps of: providing indicator areas on said wafer, said indicator areas having combinations of line widths and pattern factors violating existing ground rules of metal lines thereby said indicator areas being dished out during said polishing using a chemical-mechanical polisher to polish the metal layers to remove material therefrom, inspecting indicator areas on the wafer to determine an amount of material removed from said areas, and adjusting the operation of the chemical-mechanical polisher in response to the inspection of the indicator areas. The indicator areas may include macroblocks comprised of a multitude of individual blocks. The wafer may be inspected by optically identifying the polishing state of to blocks in the macroblock. Additionally, the process may be automated for mass production.

Abstract: A method of manufacturing self-aligned titanium salicide is provided which includes the steps of forming a LOCOS isolation region on a silicon substrate, forming a titanium layer on the surface of the silicon substrate, performing a first two-step rapid thermal anneal on the silicon substrate in an ambient filled with hydrogen and nitrogen gases to convert the titanium layer into a titanium salicide layer, selectively etching the silicon substrate to remove the titanium layer that has not reacted with the silicon substrate, and performing a second two-step rapid thermal anneal on the silicon substrate in an ambient filled with hydrogen and nitrogen gases. Each of the two-step rapid thermal anneals include a first pre-heat step and a second anneal step.