Abstract: A server computer which determines the configuration of a file for configuring a plurality of virtual computers respectively is configured to comprise: an OS/AP file evaluation criteria table which stores evaluation criteria for judging whether to split and manage a file required for the configuration of the virtual computers; a user data evaluation criteria TBL; and a verification and splitting unit which judges whether the file conforms to the evaluation criteria, and determines a part of a file judged to conform to the evaluation criteria as a first file stored as an entity and determines the remaining part of the file as a second file for referencing an entity of a predetermined destination storage.

Abstract: The present invention provides a computer implemented method, data processing system, and computer program product for mapping and dispatching virtual processors in a data processing system having at least a first partition and a second partition. The data processing system runs a first partition on a virtual processor during a first timeslice. The data processing system identifies an at least one physical page used by the first partition and the second partition. The data processing system maps the at least one physical page to the first partition and the second partition. The data processing system determines a fitness value based on the mapping. The data processing system dispatches the Virtual processor to the second partition on a second timeslice based on the fitness value, wherein the second timeslice immediately succeeds after the first timeslice, whereby the at least one physical page remains in cache during at least the first timeslice and the second timeslice.

Abstract: An application monitoring system determines the health of one or more resources used to process a transaction, business application, or other computer process. Performance data is generated in response to monitoring application execution and processed to determine and an actual and baseline value for resource usage data. Resource usage baseline data may be determined from previous resource usage data associated with a resource and particular transaction (a resource-transaction pair). The baseline values are compared to actual values to determine a deviation for the actual value. Deviation information for the time series data can be reported through an interface or some other manner.

Abstract: In a time management control method of a computer system for managing each individual time of a plurality of virtual systems, a service process or retains an overall system time and a difference time between the overall system time and a virtual system time for each virtual system, and a firmware in the virtual system acquires the overall system time and the difference time, calculates a difference time between the overall system time and the change time of the virtual system, adds the both difference times, and informs the service processor. Accordingly, the virtual system time can be changed without time management hardware in each virtual system. Further, since service processor performs update processing only, it is also possible to prevent a time set error caused by delayed calculation processing etc.

Abstract: A portable computer having a biometric authentication device is disclosed. The portable computer also includes a processor, a power supply unit having a first power system and a second power system, a power control circuit for controlling the power supply unit, and a start-up button for generating a startup signal for starting the portable computer. The biometric authentication device sends a power request signal to the power control circuit to activate the second power system upon a detection of a human user in a state where the second power system is deactivated and electric power is being supplied by the first power system. The biometric authentication device can perform an authentication operation while receiving electric power from the second power system, and the power control circuit causes the portable computer to transition to a power-on state in response to an authentication success by the biometric authentication device.

Abstract: Method and computer program product for supplying power in a computing system, and computer program product implementing the method. The method comprises monitoring power consumption of the computing system, supplying power to the computing system using only a first power supply over a first range of power consumption, and supplying power to the computing system using a combination of the first power supply and a second power supply over a second range of power consumption. The first power supply provides greater efficiency than the combination of the first and second power supplies over the first lower range of power consumption, the combination of the first and second power supplies provides greater efficiency than the first power supply over the second higher range of power consumption.

Abstract: The disclosure provides a mechanism which is activated when a user opts to hibernate their computer (at the end of the day) rather than switching it off. In particular, on receipt of a hibernate request, an embodiment provides a mechanism for determining whether (as a result of, for example, a distribution or installation of software to a computer) there are any outstanding reboot operations for the computer. If there are any outstanding reboot operations for the computer, an embodiment advises the user of the fact; and allows the user to reconsider whether or not they wish to shut the computer down (or reboot the computer), or hibernate the computer. An embodiment then reboots the computer or hibernates the computer in accordance with the user's wishes.

Abstract: This invention provides a data transfer control device for carrying out data transfer using a plurality of transfer resources. The data transfer control device comprises a transfer resource management portion that set the plurality of transfer resources to either one of a transfer-enabled state whereby data transfer is enabled and a plurality of standby states on the basis of a load on the data transfer control device and that manages the plurality of transfer resources so as to assume the set operating status; and a load distribution portion that distributes the data to transfer resources that have been set to the transfer-enabled state. The plurality of standby states are states which data transfer is disabled and which mutually differ at a minimum in terms of at least one of power consumption level and transition time to the transfer-enabled state.

Abstract: Process for management resources each resource having one or several characteristics and, for each characteristic, a given category to which the resource belongs, this process comprising the following operations: a) identify (101) one or several characteristics required for the resources, b) identify (102) a group of resources with the required characteristic(s), c) for each resource in said group, and for each characteristic of the resource, associate (103) the resource category with a time, with a value that depends on the category, d) assign (104) a magnitude in time to each resource, called adhesion, equal to the greatest time of the resource characteristics.

Abstract: Under the present solution, dependencies and relationships of objects are stored and are updatable by consumers and optionally manufacturers through a local UI or web interface. These dependencies and relationships are stored in a “collection profile” which describes the capabilities of objects. When a request to reduce energy is received the system can query the collection profile to determine the downstream effect of reducing energy to a single object. The collection profile will identify which other objects rely on that object and would also need to have energy reduced. Being able to identify these linkages and effects of changes across the system will be critical for good energy management.

Abstract: A synchronizing circuit includes an internal partial power supply interruption circuit section which can be subjected to a power supply interruption and includes a data transmission register configured to output data for controlling a power supply interruption and a clock enable control register configured to output an enable signal; an internal partial power supply interruption control circuit section configured to control a power supply interruption and includes a gated clock buffer configured to control a clock signal based on the enable signal, and a data reception register configured to take in data based on the controlled clock signal; and an isolation cell configured to output an output from the internal partial power supply interruption circuit section as a fixed value when the internal partial power supply interruption circuit section has been subjected to a power supply interruption.

Abstract: Various technologies and techniques are disclosed for propagating resources during a distributed build process. Subscription of interest is registered in resources needed during a distributed build process. Build data is analyzed to determine what resources will be needed. The subscriptions of interest are stored in a data store that is accessible by all build machines participating in the distributed build process. A status of subscriptions of interest is monitored in the data store. When the status of respective subscriptions of interest indicates that a publication notice was registered for a respective resource, the respective resource is retrieved from a machine that contains the resource. When a new resource is created that is needed by other build machines, a publication notification is registered with the data store so the other build machines can determine that the new resource is now available.

Abstract: Systems and methods for transferring data using a ring bus architecture in a system that implements multi-phase clocking. In one embodiment, the system is a multiprocessor having multiple processor cores coupled to the ring bus. The bus may be a bidirectional bus having a first data path on which data is transferred in a clockwise direction and a second data path on which data is transferred in a counterclockwise direction. Controllers within the processor cores provide phase-shifted signals to the latches to clock data into them. Data transfers on the bus may be controlled by an arbiter which is coupled to the processor cores' controllers. The arbiter may schedule data transfers on the bus based on data transfer speeds associated with left-to-right and right-to-left data transfer directions. The arbiter may cause the phases of the clock signals to be selectively varied, or may cause the clock signals to be gated.

Abstract: A memory controller performs a read test for each of a plurality of memory devices to generate a read delay time of each memory device. There is a prime memory device and a subset of memory devices. For each memory device of the subset, the read delay time for the prime memory device is compared with the read delay time of each memory device of the subset of memory devices to generate a differential delay for each memory device of the subset. For each subset memory device, a write test start time of the prime memory device is combined with a differential delay of each memory device to generate a write test start time for the each memory device. A write test for each memory device uses the write test start time for each subset memory device to generate a write launch time for each subset memory device.

Abstract: In scheduling shared processing that has a higher priority than LPAR processing, giving precedence to physical CPUs running idle LPARs prevents prolonged hold-up of LPAR processing. In a system is comprised of multiple physical CPUs, multiple LPARs to which these physical CPUs are allocated and which execute programs under their guest OSes, and a management program managing these LPARs, a few additional units are introduced: a guest OS monitoring unit that can grasp the states of guest OSes running on these LPARs and a dispatcher unit that allocates one of these physical CPUs to shared processing requested by the management program, which has a higher priority than LPAR processing. When a request for shared processing arises, the dispatcher unit interrogates the guest OS monitoring unit and, based on the information obtained from it, gives priority of allocation to the physical CPU processing an idle LPAR.

Abstract: Methods and apparatus for re-acquiring a WiMAX network after a relatively long power saving mode (e.g., sleep or idle mode) using a “pre-wakeup” scheme are provided. According to this pre-wakeup scheme, a mobile station (MS) may power up receiving circuitry to search for the current channel or, if unsuccessful, a neighbor channel. After a successful network search during sleep mode, the MS may return to sleep for the remainder of the sleep window until the circuitry is powered up a second time to wakeup and then listen for an expected message. By pre-waking up and searching before waking up for the expected message, the MS may counteract the effects of the potential error in the local oscillator frequency accumulated during the long sleep mode. In this manner, the message miss rate may be reduced, thereby saving power and extending the time in which the MS may operate between battery rechargings.

Abstract: A memory controller, a method of testing memory power management modes in an integrated circuit and an integrated circuit. In one embodiment, the memory controller includes a power management mode test controller couplable to a test access port and at least one memory core and configured to respond to a signal provided via the test access port by providing an ordered signal-setting sequence to the at least one memory core to cause the at least one memory core to enter into and exit from at least one memory power management mode.

Abstract: A power management method for a multi-microprocessor system is provided. The multi-microprocessor system comprises a first microprocessor and a second microprocessor. The power management method comprises steps of receiving a power down instruction; transmitting a power down notice signal to the first microprocessor from the second microprocessor, transmitting a reply signal from the first microprocessor to the second microprocessor in response to the power down notice signal, and turning off power of the first microprocessor by the second microprocessor.

Abstract: Some aspects include reception of a command from one of a chassis management module and a BIOS specifying a data region to be updated and a locking policy, determination of whether the data region is locked, implementation of the locking policy and returning of a session lock handle if it is determined that the data region is not locked, reception, from the one of the chassis management module and the BIOS, of data for updating the data region, the session lock handle, and an offset, determination that the session lock handle is associated with the data region, writing of the data to the data region at the offset, reception of a request for data of the updated data region from the other one of the chassis management module and the BIOS, determination of whether the updated data region is locked, and if it is determined that the updated data region is not locked, providing of the data of the updated data region to the other one of the chassis management module and the BIOS.

Abstract: A method, device, and system are disclosed. In one embodiment the method includes causing a processor to enter into a first power state. Then an interrupt is received that signals the processor to leave the first power state. The method continues by causing the processor to remain in the first power state if the interrupt was received less than a minimum dwell time after the processor entered the first power state.