Abstract: A substrate strip with warpage-preventive linkage structure is proposed for a BGA (Ball Grid Array) application. The proposed substrate strip is composed of a series of substrates, each being used for the construction of an individual unit of a BGA package, and which is characterized by the provision of a warpage-preventive linkage structure, by which each substrate on the substrate strip is supported by means of no more than two tie bars, i.e., either by a two-point linkage structure or a one-point linkage structure, in contrast to the four-point linkage structure utilized by the prior art. During high-temperature fabrication steps when the substrate is subjected to thermal stresses, the substrate can freely expand toward the corners where no tie bars are provided; and consequently, it can be unwarped by the thermal stresses. This unwarped substrate allows the subsequently implanted ball grid array thereon to have high coplanarity.

Abstract: In a semiconductor device including active areas where transistors are formed and a field area for isolating the active areas from each other, the field area has a plurality of dummy areas where dummy gates are formed.

Abstract: A photo-detector comprises a photo-absorptive region (1) which absorbs individual incident photons to produce corresponding electron-hole pairs. A bias (Vb) applied by an electrode (3) to the region 1 separates the oppositely charged electrons and holes such that the individual electrons apply a gate field to an electrometer (4) in the form of a single electron transistor which has a source-drain path (6) along which carrier charged transport is limited Coulomb blockade. The charge of the individual, photo-induced electrons (e) modulate charge carrier transport through the single electron transistor and the resulting current is detected by amplifier (A1) to produce an voltage output (Vout) so as to detect incident photons individually.

Abstract: Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is employed a doped polysilicon floating gate electrode having an central annular portion having a higher dopant concentration than a peripheral annular portion of the doped polysilicon floating gate electrode. The higher dopant concentration within the central annular portion of the doped polysilicon floating gate electrode provides enhanced programming speed properties of the split gate field effect transistor (FET) device. The lower dopant concentration within the peripheral annular portion of the doped polysilicon floating gate electrode provides enhanced erasing speed properties within the split gate field effect transistor (FET) device under certain circumstances of fabrication of the split gate field effect transistor (FET) device.