Abstract: A semiconductor package is provided. A semiconductor package includes a wiring structure, which includes a first insulating layer and a first wiring pad inside the first insulating layer a semiconductor chip on the wiring structure, an interposer having one surface facing the semiconductor chip and including a second insulating layer and a second wiring pad inside the second insulating layer, a connecting member connecting the first wiring pad and the second wiring pad, a support member in the first recess and between the wiring structure and the interposer, and a mold layer covering the semiconductor chip. One surface of the wiring structure includes a first recess exposing at least a part of the first insulating layer.

Abstract: A semiconductor device structure includes a first hard mask pattern disposed over a metal layer. The semiconductor device structure also includes a second hard mask pattern disposed over the metal layer and spaced apart from the first hard mask pattern. A bottom surface of the first hard mask pattern is coplanar with a bottom surface of the second hard mask pattern.

Abstract: A method of manufacturing a semiconductor device includes the following. A core material layer and a patterned mask layer are formed above a target layer. A first spacer layer is formed and a first treatment process is performed to form a treated first spacer layer. A first removal process is performed on the treated first spacer layer and the patterned mask layer to form multiple first spacers. The core material layer is patterned to form a core layer using the first spacers as a mask. A second spacer layer is formed and a second treatment process is performed to form a treated second spacer layer. A second removal process is performed on the treated second spacer layer and the core layer to form multiple second spacers. A pattern of the second spacers is transferred to the target layer to form a patterned target layer.

Abstract: A display apparatus includes a driving backplane, a first bank layer, light-emitting elements, a second bank layer, light adjusting patterns, a light-shielding pattern layer and color filter patterns. The color filter patterns includes first color filter patterns having the same color. The light-emitting elements include first light-emitting elements respectively overlapping the first color filter patterns. The light adjusting patterns include first color conversion patterns respectively overlapping the first color filter patterns. A center wavelength of one of the first light-emitting elements is greater than a center wavelength of another one of the first light-emitting elements, and a thickness of one of the first color conversion patterns is greater than a thickness of another one of the first color conversion patterns.

Abstract: A light-emitting device includes a light-emitting element including an epitaxial structure and a DBR. The DBR includes first and second reflective units. The first reflective unit includes first reflective structures. The second reflective unit includes second reflective structures. Each of the first and second reflective structures has first and second material layers. The first material layer of each of the first reflective structures has an optical thickness different from that of the first material layer of each of the second reflective structures. The second material layer of each of the first reflective structures has an optical thickness different from that of the second material layer of each of the second reflective structures. In each of the first and second reflective structures, the first material layer has a refractive index different from that of the second material layer.

Abstract: In an embodiment, a method of forming a semiconductor device includes: forming a first oxide layer over a semiconductor fin structure; performing a first nitridation process to convert the first oxide layer to an oxynitride layer; depositing a silicon-containing layer over the oxynitride layer; performing a first anneal on the silicon-containing layer, wherein after performing the first anneal, the oxynitride layer has a higher nitrogen atomic concentration at an interface with the semiconductor fin structure than in a bulk region of the oxynitride layer; and forming a dummy gate structure over the silicon-containing layer.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to glass layers within a package that include one or more high aspect ratio TGV that are filled with conductive material. The TGV extends from a first side of the glass layer to a second side of the glass layer opposite the first side and are filled with conductive material to provide a high-quality electrical connection between the first side of the glass layer and the second side of the glass layer, where a portion of the wall of the TGV includes titanium. Other embodiments may be described and/or claimed.

Abstract: A transient voltage suppressing (TVS) device including a first silicon-controlled rectifier and a voltage clamp having a first terminal and a second terminal. The first terminal is connected to a cathode of the first silicon-controlled rectifier.

Abstract: A method of manufacturing a semiconductor device includes providing a stack including interlayer sacrifice layers and interlayer insulation layers stacked alternatively. The stack includes a core region and a periphery region distributed along a first direction. The method also includes forming a gate line slit penetrating the stack and extending along the first direction. The gate line slit includes a first slit and a second slit interconnected with each other. The periphery region includes the first slit. The core region includes the second slit. The width of the first slit along the second direction is greater than the width of the second slit along the second direction. The second direction intersects with the first direction. The method further includes forming an isolation section in at least the first slit.

Abstract: The present disclosure discloses a storage cell, a storage block and a memory. The storage cell includes a semiconductor assembly, a controlling gate, and at least one base electrode. The semiconductor assembly includes a source-region semiconductor, a drain-region semiconductor and a channel semiconductor. The channel semiconductor is arranged between the source-region semiconductor and the drain-region semiconductor, and is arranged side by side with the source-region semiconductor and the drain-region semiconductor. The controlling gate is arranged at one side of the semiconductor assembly, and corresponds to the channel semiconductor. The at least one base electrode is electrically connected to the other side of at least one of the source-region semiconductor and the drain-region semiconductor, corresponds to the at least one of the source-region semiconductor and the drain-region semiconductor, and is configured to be applied a base voltage.

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three-dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by single crystalline silicon (Si) channel regions. The single crystalline silicon (Si) channel regions can include a dielectric material to provide support structure to the single crystalline channel regions when forming the horizontal access devices in vertical three-dimensional (3D) memory. Horizontally oriented access lines can connect to gate structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.

Abstract: A semiconductor device of embodiments includes: a die pad; a semiconductor chip fixed on the die pad; and a sealing resin covering the semiconductor chip and at least a part of the die pad. The sealing resin has a first protruding portion provided on one side surface and a second protruding portion provided on another side surface. The cross-sectional area of the first protruding portion is equal to or more than 10% of the maximum cross-sectional area of the sealing resin. The cross-sectional area of the second protruding portion is equal to or more than 10%; of the maximum cross-sectional area. The maximum cross-sectional area is equal to or more than 6 mm2.

Abstract: A semiconductor device includes a substrate; a first stack structure including first gate electrodes on the substrate; and a second stack structure on the first stack structure; wherein the first stack structure includes a first lower staircase region, a second lower staircase region, and a third lower staircase region, wherein the second stack structure includes a first upper staircase region, a second upper staircase region, a third upper staircase region, and at least one through portion penetrating the second stack structure and on the first to third lower staircase regions, wherein the first lower staircase region has a same shape as a shape of the first upper staircase region, the second lower staircase region has a same shape as a shape of the second upper staircase region, and the third lower staircase region has a same shape as a shape of the third upper staircase region.

Abstract: Embodiments of present invention provide a magnetic tunnel junction (MTJ) structure. The MTJ structure includes a MTJ stack, the MTJ stack including a tunnel barrier layer on a reference layer and a free layer on the tunnel barrier layer, wherein the free layer includes multiple sub free layers, the multiple sub free layers being multiple ferromagnetic strips placed parallel to each other on the tunnel barrier layer, the multiple ferromagnetic strips having respective first ends connected to a first electrode and respective second ends connected to a second electrode. A method of forming the MTJ structure is also provided.

Abstract: An image sensor includes a pixel array, a color filter array including a plurality of color filters arranged in a matrix on the pixel array, and a micro lens array arranged on the color filter array. The plurality of color filters are divided into a plurality of groups that each include nine color filters arranged in three rows and three columns. A plurality of first color filters among the nine color filters included in each group of the plurality of groups face one another in a diagonal direction, and a plurality of second color filters among the nine color filters included in each group of the plurality of groups respectively include identical color filters corresponding to a corresponding group of the plurality of groups.

Abstract: A memory device and a manufacturing method thereof are disclosed in the present invention. The memory device includes a substrate, trenches, an oxide semiconductor layer, a gate dielectric layer, and word line structures. The substrate includes active regions and an isolation structure located between the active regions. The active regions contain silicon. The trenches are disposed in the active regions and the isolation structure. The oxide semiconductor layer is disposed in each trench. The gate dielectric layer is disposed on the oxide semiconductor layer and located in each trench. The word line structures are disposed on the gate dielectric layer and located in the trenches, respectively. At least a portion of the gate dielectric layer is disposed between the oxide semiconductor layer and each word line structure.

Abstract: Processes for producing an OLED screen with a reduced size, in particular for an aircraft. The processes utilize laser cutting to reduce the size of OLED screens from a production line. After the cutting, a plasma coating process seals the cut edges. The portion of the production OLED screen that is cut may be a portion of the display screen. The screens with the reduced sized may be installed in an aircraft, and, two or more of the OLED screens with reduced sized may be positioned adjacent to each other so as to form an array.

Abstract: An image sensing device includes a first substrate including a first surface and a second surface facing away from the first surface, the first substrate including a pixel region and a pad region located outside the pixel region, the pixel region being structured to include pixel that generate electrical signals based on light incident upon the first surface to reach to the pixels, an insulation layer disposed under the second surface and including interconnects and an electrode pad, a pad open region disposed in the pad region and structured to expose the electrode pad, and a substrate isolation layer disposed outside the pixel region in the first substrate and formed to penetrate the first substrate. The substrate isolation layer includes a lens material.

Abstract: The present disclosure provides a high-density three-dimensional multilayer memory and a fabrication method, and relates to the preparation technology of memories. The memory comprises an underlying circuit part and a basic structure body disposed above the underlying circuit part, wherein the basic structure body is divided into two independent interdigitated structures by a curve-shaped division groove, at least three memory cell holes are formed in the curve-shaped division groove side by side, a vertical electrode is disposed in each memory cell hole, and the memory medium is an insulating medium; and a buffer region is placed on the inner wall of the memory cell hole and at the position of a first conducting medium layer, the buffer region protrudes from the inner wall of the memory cell hole to the central axis of the memory cell hole, and the buffer region is connected to the memory medium.

Abstract: A method for manufacturing a photodetection device, which includes the following steps: making a cadmium-rich structured coating, over a substrate of CdxHg1-xTe, and using a first etching mask; etching to enlarge the through openings of the first etching mask or the through openings of an interlayer etched with the structured coating, so as to form a second etching mask; injecting acceptor doping elements into the substrate, throughout the second etching mask, and activating and diffusing the acceptor doping elements to form at least one P doped region in the semiconductor substrate; selective interdiffusion annealing of cadmium, so as to form in each P doped region a cadmium-rich concentrated well with a cadmium concentration lateral gradient; and making at least one electrical contact pad, at each through opening in the structured coating.