Abstract: A optical sensing device includes a substrate, an optical acting area and a filter layer. The optical acting area is disposed on the substrate. The filter layer covers the optical acting area and selectively allows only a light beam with a specific wavelength to pass through and be received by the optical acting area while blocking the light beams with other wavelengths. Each of the two sides of the substrate has a bevel structure. The filter layer covers each bevel structure of each side to prevent the light beams with other wavelengths from passing through the two sides of the substrate being received by the optical acting area.

Abstract: A semiconductor package includes: a first substrate; a second substrate including a semiconductor element formed thereon; a film layer between the first substrate and the second substrate; and a molding member surrounding the second substrate, wherein the film layer includes a crystalline spherical silica filler distributed in a matrix.

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of monolithic wafers and disaggregated integrated circuit (IC) dies, adjacent layers being coupled together by first interconnects having a pitch less than 10 micrometers between adjacent first interconnects, the disaggregated IC dies arranged with portions of the monolithic wafers into modular sub-assemblies; and a package substrate coupled to the modular sub-assemblies by second interconnects having a pitch greater than 10 micrometers between adjacent second interconnects. The disaggregated IC dies are surrounded laterally by a dielectric material, and the disaggregated IC dies are arranged with portions of the monolithic wafers such that a voltage regulator circuit in a first layer of the plurality of layers, a compute circuit in a second layer of the plurality of layers, and a memory circuit in a third layer of the plurality of layers are conductively coupled together in an intra-modular power delivery circuitry.

Abstract: A semiconductor device includes a semiconductor chip having a semiconductor integrated circuit. A cooling channel is formed in the semiconductor chip. At least a portion of the cooling channel is formed in the semiconductor chip. First wick structures may be arranged on a bottom of the cooling channel that is parallel to an upper surface of the semiconductor chip in a transverse direction. The first wick structures may move a liquid coolant by capillary action in the transverse direction along the bottom of the cooling channel. Second wick structures may be arranged along an inner surface of the vapor chamber and may move the liquid coolant by capillary action in the transverse direction along the inner surface of the vapor chamber.

Abstract: Disclosed is a semiconductor device comprising a peripheral circuit structure on a first substrate, a cell array structure on the peripheral circuit structure, and a backside structure on the cell array structure. The cell array structure includes a stack structure including gate electrodes and interlayer dielectric layers that are alternately stacked, through plugs that extend in a first direction through the stack structure and each including a first surface adjacent to the backside structure and a second surface opposite to the first surface, a middle circuit structure between the stack structure and the peripheral circuit structure and connected to the peripheral circuit structure, and a connection plug connected to the middle circuit structure and the backside structure. The through plugs include a first through plug connected through the first surface to the backside structure, and a second through plug connected through the second surface to the middle circuit structure.

Abstract: A junction field effect transistor device includes a substrate, a well region, a first top layer, a plurality of source/drain regions, a first isolation structure, a gate, and a plurality of first well slots. The substrate has a first conductivity type. The well region is embedded in the substrate. The well region has a second conductivity type. The first top layer is embedded in the well region. The first top layer has the first conductivity type. The source/drain regions are disposed on a top surface of the well region. The first isolation structure is adjacent to one of the source/drain regions. The gate is disposed on a top surface of the first top layer. The first well slots are disposed below the gate. A second-conductivity-type dopant concentration of the first well slots is lower than a second-conductivity-type dopant concentration of the well region.

Abstract: A method to electrically couple a capacitor to an active silicon region of a memory structure includes: providing a substrate including the memory structure; performing deposition and etch cycles to remove a portion of one or more dielectric layers from the substrate, enlarge a trench between adjacent bitline structures, and provide access to at least one of a polymer layer or a dielectric layer adjacent to an upper portion of the active silicon region; performing a breakthrough operation including etching the polymer layer or the dielectric layer in the trench to expose the upper portion of the active silicon region; and performing an over-etch operation to remove the upper portion of the active silicon region to provide access for electrically coupling the capacitor to a remaining lower portion of the active silicon region. The over-etch operation is distinct from the breakthrough operation.

Abstract: A pixel structure for an electronic display, the pixel structure comprising a substrate, at least one LED emitter arranged on the substrate, and at least one wavelength conversion unit arranged on the substrate adjacent to the LED emitter. The LED emitter is configured to emit emission radiation, the emission radiation being within an emission wavelength range and emitted in one or multiple emission directions within a main emission plane. The wavelength conversion unit is configured to convert the emission radiation to converted radiation within a converted wavelength range, the converted wavelength range being different from the emission wavelength range. The converted radiation propagates from the wavelength conversion unit in a main conversion direction perpendicular to the main emission plane, the main conversion direction being, for example, a direction towards a user of an electronic device having an electronic display comprising at least one such pixel structure.

Abstract: This display device includes a first light-emitting element and a second light-emitting element connected in series, and a third light-emitting element and a fourth light-emitting element connected in series. The first light-emitting element and the second light-emitting element share a second electrode formed in an upper layer above a first light-emitting layer and a second light-emitting layer, and the third light-emitting element and the fourth light-emitting element share a fourth electrode formed in an upper layer above a third light-emitting layer and a fourth light-emitting layer. The second electrode is an island-shaped electrode and functions as a cathode of one of the first light-emitting element and the second light-emitting element and an anode of the other, and the fourth electrode is an island-shaped electrode and functions as a cathode of one of the third light-emitting element and the fourth light-emitting element and an anode of the other.

Abstract: The present disclosure provides a display panel, a manufacturing method thereof, and a display apparatus. The display panel includes a display area, provided with at least one to-be-dug area; and an annular isolation area, surrounding the to-be-dug area, and arranged between the to-be-dug area and the display area surrounding the to-be-dug area, the annular isolation area includes a first annular blocking dam surrounding the to-be-dug area. The display panel includes: a base substrate, an electroluminescent layer, an encapsulation layer and a filling layer. An orthographic projection of the filling layer on the base substrate is within a range of orthographic projections of the to-be-dug area and the annular isolation area on the base substrate.

Abstract: Techniques are provided for protecting integrated circuits from plasma-induced electrostatic discharge (ESD) using a carrier substrate with integrated junctions. According to some embodiments, the various metal features within an interconnect region above a plurality of semiconductor devices are electrically coupled to one or more conductive pads on a bonded carrier substrate. The conductive pads provide a contact to underlying doped regions within the carrier substrate that form one or more PN junctions. This provides the ability to electrically ground metal features in the interconnect region via the carrier substrate. Formation of additional interconnect layers such as those provided during far back end of line (FBEOL) processing, can proceed while causing less plasma-induced ESD damage to the integrated circuit, because the interconnect region is connected to ground of carrier substrate by way of PN junctions, thus providing a discharge path for charge that develops during subsequent processing.

Abstract: A semiconductor memory device includes a peripheral gate structure disposed on a substrate, a bit line disposed on the peripheral gate structure and extending in a first direction, a shielding structure disposed adjacent to the bit line on the peripheral gate structure and extending in the first direction, a first word line disposed on the bit line and the shielding structure and extending in a second direction, a second word line disposed on the bit line and the shielding structure, extending in the second direction, and spaced apart from the first word line in the first direction, first and second active patterns disposed on the bit line and disposed between the first and second word lines, and contact patterns connected to the first and second active patterns.

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a semiconductor device. The semiconductor device includes a substrate including a plurality of fins, a plurality of semiconductor nanosheets stacked on the plurality of fins, a plurality of gate stacks wrapping the plurality of semiconductor nanosheets, an isolation structure around the plurality of fins, and a separator structure on the isolation structure to separate the plurality of gate stacks from each other. The separator structure includes a body and a cap on the body. The cap includes a first portion and a second portion. Sidewalls and bottom of the second portion is wrapped by the first portion.

Abstract: A light-emitting element comprises a core comprising a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer, and an emissive layer provided between the first semiconductor layer and the second semiconductor layer, and a first element insulating film around a side surface of the core, wherein the first element insulating film comprises a composite of an insulating member and an elastic member.

Abstract: A semiconductor package is provided. A semiconductor package includes a wiring structure, which includes a first insulating layer and a first wiring pad inside the first insulating layer a semiconductor chip on the wiring structure, an interposer having one surface facing the semiconductor chip and including a second insulating layer and a second wiring pad inside the second insulating layer, a connecting member connecting the first wiring pad and the second wiring pad, a support member in the first recess and between the wiring structure and the interposer, and a mold layer covering the semiconductor chip. One surface of the wiring structure includes a first recess exposing at least a part of the first insulating layer.

Abstract: A semiconductor device structure includes a first hard mask pattern disposed over a metal layer. The semiconductor device structure also includes a second hard mask pattern disposed over the metal layer and spaced apart from the first hard mask pattern. A bottom surface of the first hard mask pattern is coplanar with a bottom surface of the second hard mask pattern.

Abstract: A method of manufacturing a semiconductor device includes the following. A core material layer and a patterned mask layer are formed above a target layer. A first spacer layer is formed and a first treatment process is performed to form a treated first spacer layer. A first removal process is performed on the treated first spacer layer and the patterned mask layer to form multiple first spacers. The core material layer is patterned to form a core layer using the first spacers as a mask. A second spacer layer is formed and a second treatment process is performed to form a treated second spacer layer. A second removal process is performed on the treated second spacer layer and the core layer to form multiple second spacers. A pattern of the second spacers is transferred to the target layer to form a patterned target layer.

Abstract: A display apparatus includes a driving backplane, a first bank layer, light-emitting elements, a second bank layer, light adjusting patterns, a light-shielding pattern layer and color filter patterns. The color filter patterns includes first color filter patterns having the same color. The light-emitting elements include first light-emitting elements respectively overlapping the first color filter patterns. The light adjusting patterns include first color conversion patterns respectively overlapping the first color filter patterns. A center wavelength of one of the first light-emitting elements is greater than a center wavelength of another one of the first light-emitting elements, and a thickness of one of the first color conversion patterns is greater than a thickness of another one of the first color conversion patterns.

Abstract: A light-emitting device includes a light-emitting element including an epitaxial structure and a DBR. The DBR includes first and second reflective units. The first reflective unit includes first reflective structures. The second reflective unit includes second reflective structures. Each of the first and second reflective structures has first and second material layers. The first material layer of each of the first reflective structures has an optical thickness different from that of the first material layer of each of the second reflective structures. The second material layer of each of the first reflective structures has an optical thickness different from that of the second material layer of each of the second reflective structures. In each of the first and second reflective structures, the first material layer has a refractive index different from that of the second material layer.

Abstract: In an embodiment, a method of forming a semiconductor device includes: forming a first oxide layer over a semiconductor fin structure; performing a first nitridation process to convert the first oxide layer to an oxynitride layer; depositing a silicon-containing layer over the oxynitride layer; performing a first anneal on the silicon-containing layer, wherein after performing the first anneal, the oxynitride layer has a higher nitrogen atomic concentration at an interface with the semiconductor fin structure than in a bulk region of the oxynitride layer; and forming a dummy gate structure over the silicon-containing layer.