Abstract: An encoder encodes digital signals representative of data by classifying the digital signals into first and second classes indicative of their influence on data quality and subjects them to error detection encoding capable of generating at least two error detection codes which respectively correspond to the first and second classes. A decoder receives the encoded digital signals classified into first and second digital signal classes, decodes the error detection codes, and generates error signals, corresponding to the respective digital signal classes, from which the quality of the received digital signals is estimated and the utility of the received digital signals is determined.

Abstract: An automatic self-testing system includes a plurality of sensor processing channels or paths each having a sensor for providing, either directly or indirectly, a digital value to a comparator which compares the measured value with predetermined value that is, in turn, provided to coincidence logic that evaluates the output of its comparator with the output of the comparators of the other paths to provide an output indicative of a pass/fail condition. Each sensor processing path includes two sub-paths that can be associated with or switched into the processing path while the disassociated sub-path undergoes off-line testing by a test processor. Testing is effected by providing a digital value to the sub-path under test while sensing the output to determine the functional validity of the sub-path under test. The combinational logic state of the system is monitored and converted into a decimal value that is compared with the set of decimal values corresponding to the finite known-good logic states of the system.

Abstract: A testing system evaluates one or more integrated circuit chips using RF communication. The system includes an interrogator unit with a radio communication range, and an IC chip adapted with RF circuitry positioned remotely from the interrogator unit, but within the radio communication range. The interrogator unit transmits a power signal to energize the IC chip during test procedures, and interrogating information for evaluating the operation of the IC chip. Test results are transmitted by the IC chip back to the interrogator unit for examination to determine whether the IC chip has a defect. In this manner, one or more IC chips can be evaluated simultaneously without physically contacting each individual chip.

Abstract: A JTAG Boundary Scan method by which the on-chip system logic (OCSL) of an integrated circuit is changed by use of a state machine which, among other functions, allows a predefined set of instructions to be loaded into an Instruction Register and then executed. The predefined instructions are designed to follow in sequence after certain other previous instructions. The instructions change the OCSL from one state to another state and allows the state to be changed without the need of a full device reset. Additional instructions within this invention were created to have attendant operating modes for which termination is self timed within the integrated circuit. Additional instructions further control the implementation of instruction execution within the state machine.

Abstract: A system decoder having error correcting memories for high-speed data transmission and a method for controlling the same. A system decoder of an optical disk reproducing apparatus having a descrambler for restoring scrambled data in the process of encoding data, includes first and second memories for correcting an error, and a memory controller for transmitting error-corrected data to the descrambler while data read and demodulated from the optical disk is written in one of the first and second memories, and error-correcting data written in the other memory while the demodulated and error-corrected data is written and read.

Abstract: The present invention is embodied in a method and apparatus which provides a ROM embedded in an DRAM utilizing unused portions of the DRAM. By hardwiring the unused digitlines of the DRAM to either a specified voltage or ground, the outputs of the sense amplifiers associated with those unused digitlines can be programmed to output a specific logic state. By combining the outputs from several sense amplifiers, a fixed bit pattern can be produced. The fixed bit pattern can be used, for example, to generate a test data pattern for a Built-in Self Test or to generate an initialization sequence.

Abstract: A pattern generator for an integrated circuit tester includes an instruction memory storing addressable instructions (INST) and reading out each instruction when addressed by an address (ADDR) supplied as input thereto. An instruction processor receives each instruction read out of the instruction memory and alters the address input to the instruction memory in accordance with the received instruction so that the instruction memory reads out a next instruction. The instruction processor, which includes a conventional return address stack, is capable of executing conventional address increment, call and return instructions. The instruction processor is also capable of executing a temporary return instruction (TEMP) by incrementing its current address output to produce a new return address, by setting its address output to the value of a return address previously saved in the stack, by popping the saved return address from the stack, and by pushing the new return address onto the stack.

Abstract: The address data acquiring section causes the format information storage section to store the format information concerning the allocation of addresses to the blocks of a code to be read out and the plural addresses provisionally determining section restores the address data from each of two or more than two blocks found in a picked up image and detected by the block detecting section. Then, it causes the address determining section to determine the correct address of each of the blocks according to the provisionally determined address data for the two or more than two blocks and the format information stored in the format information storage section. The information data reproducing section rearranges and reproduces the block data restored from the blocks detected by the block detecting section and restored by the block data restoring section according to the address information determined by the address determining section.

Abstract: An encoding/decoding system for RAID-6 or multiple track tape systems uses one of a selected set of values for m, with m+1 prime and the field GF(2.sup.m) generated by the irreducible polynomial:g(x)=x.sup.m +x.sup.m-1 + . . . +x.sup.2 +x+1.The system performs Galois Field multiplication operations as a combination of cyclic shifting and exclusive-OR operations, and determines multiplicative inverses of weight one, two and three (m+1)-bit symbols by raising various (m+1)-bit symbols to selected powers of two. Using this system, the value of m may be chosen to be as large as or larger than the sector or tape block, and the encoding and decoding is performed once per sector or block.

Abstract: An integrated circuit containing a data processing system with a number of external peripheral pins utilizes the peripheral pins for both testing the corresponding peripherals and for parallel testing of other complex functions in a MCU. The MCU has a plurality of test modes that can be selected, with different peripheral pins being connected to a test circuit depending on which test mode is selected. This allows testing of peripherals via their corresponding pins, as well as other complex functions without the necessity of having dedicated test pins.

Abstract: A method and system in a data processing system are disclosed for the retransmission of only a portion of a data packet which had originally been transmitted incorrectly. A first data link is established between a first computer system and a second computer system. In response to the establishment of the first data link, a second data link is established between the first and second computer systems, whereby the first and second data links are related. A plurality of data packets are transmitted from the first computer system to the second computer system utilizing the first data link. Each of the data packets includes a plurality of segments. A determination is made whether each of the plurality of data packets is received correctly. In response to a determination that one of the plurality of data packets is received incorrectly, a portion of the data packet which was transmitted incorrectly is determined.

Abstract: A method and apparatus for identifying defective cells in a memory array includes receiving a request for accessing an address and analyzing the address to determine when the address matches an address stored in a temporary memory array. When the address does not match any address stored in the temporary memory array, a wait instruction is sent to a processor and the address is analyzed to determine which portion of compressed data stored in a map memory array to decompress. The map memory array stores data containing compressed addresses of defective cells in a first memory array. The portion of compressed data is then decompressed to provide expanded data when the address does not match any address stored in the temporary memory array. The expanded data are then written to the temporary memory array, and the expanded data are compared to the address to determine when the address corresponds to an expanded datum of the expanded data.

Abstract: A transceiver device having a forward error correction decoder providing at least one forward error correction metric and a data integrity monitor providing at least one automatic retry query metric to a data processor or CPU. The data processor or CPU is responsive to the forward error correction metric and the automatic retry query metric and has outputs providing a forward error correction value and an automatic retry query value to the forward error correction/data encoder and decoder.

Abstract: A data recording method error-correction-code (ECC)-encodes and modulates data of a file to be recorded in units of data blocks, and records the encoded and modulated data on a digital versatile disk-random access memory (DVD-RAM). Dummy data is added to make a last data block when the size of a file to be recorded is not an integer multiple of a data block, and then the last data block is ECC-encoded and modulated for recording the same on a DVD-RAM. The recording of data is performed in a recording region of a DVD-RAM where no data is recorded, and also starts from a recording region just next to the last data even when the last data of the previously recorded file includes dummy data.

Abstract: A memory device is described which includes a latch circuit for latching a normally externally provided signal during a test mode. The input pin which is normally enabled to receive the external signal is re-routed to provide an external reference voltage, Vref, to internal circuitry. During testing operations the external Vref signal is used. Once an integrated circuit is determined to be good, an internal generator circuit is set to provide Vref. The integrated circuit can be a flash memory device, and the input pin can be a BYTE command pin. This method of substituting the source of Vref eliminates time required to set the internal generator circuit in defective memory devices.

Abstract: A memory circuit, provided with address signal generating arrangement that includes first counter 72 for outputting first output data Q1 sequentially designating address signals for memory cells under test in a memory 10, a second counter 74 for outputting second output data Q2 used to designate address signals for each memory cell of the memory 10 for every cell under test, an output control circuit 76 for selectively outputting the second output data Q2 as third output data Q3 depending on a control signal INH, and a computing circuit 78 for carrying out computations based on the first output data Q1 and the third output data Q3, and generating address signals Q4. In this way, a memory receives address signals based on a test pattern, and a tester exclusively for memory tests is not required.

Abstract: A method of operating an integrated circuit (IC) tester is disclosed in which an IC is repeatedly tested with respect to a limited number of combinations of values of two variable IC operating parameters (X and Y) to determine the boundary of a two-dimensional range of combinations of values of the X and Y parameters for which the IC passes a test. After finding a combination of X and Y parameter values on the boundary, each combination of parameter values to be tested thereafter is selected by altering either the X or Y parameter value, with the decision based on whether the IC passed the last test and on the manner in which a last tested combination of X and Y parameter values was selected.

Abstract: A method for identifying intercell defects in a memory device activates a plurality of spaced-apart rows simultaneously. Each of the rows includes cells that are written to logic states corresponding to high voltages. Cells in rows adjacent to the activated rows are written to logic states corresponding to low voltages. After the rows are activated, a testing interval passes to allow charge from cells of the activated rows to leak to adjacent cells through any stringers or other defects. In a device according to the invention, a variable voltage level circuit is incorporated in a precharge and equalization circuit to allow both inverting and non-inverting digit lines of the memory array to be set at the same voltage levels. Because the inverting and non-inverting digit lines are held at the same voltage levels, the number of word lines that can be activated for testing is increased, thereby reducing the overall time for testing.

Abstract: A test circuit for DC testing which has a simple layout design and never causes malfunction due to simultaneous change of outputs includes test circuits connected to inputs of output allowable buffers. The test circuits are connected in a circle so that a value retained in each circuit can be applied to the adjacent test circuit. In the DC testing using the test circuit for DC testing, values which are retained in and output from output allowable buffers are circulated between the output allowable buffers. At the time, the values retained in the test circuit are changed within the range of the number allowable for simultaneous change.

Abstract: An input interface circuit is provided. The circuit includes an input transistor for receiving a digital input signal, a circuit for generating a reference value, and an integrating capacitor connected in series to a pair of current conducting electrodes of the input transistor for integrating the input signal. A logic level of the input signal is discriminated by comparing an integration of the input signal with the reference value. To provide a testing function, a test transistor is connected to a junction between the pair of current conducting electrodes of the input transistor and the integrating capacitor so that a current driving capability may be determined. Additionally, a discharge path circuit for controllably discharging the integrating capacitor is connected to the junction between the input transistor and the integrating capacitor.