Abstract: A driver includes a delay-time adjuster. A data clock is inputted to the delay-time adjuster through a data-clock signal line. While receiving input of a load signal that is a sampling signal of a second register, the delay-time adjuster adjusts a delay time of the data clock so that a phase difference between the data clock and gradation data inputted into a first register through a gradation-data signal line can be set to a predetermined value. After the completion of the input of the load signal, the delay-time adjuster holds a data clock for the adjusted delay time, and outputs the delayed data clock as a shift clock for a shift register.