Abstract: A data processing system comprises a microprocessor having a burst mode transfer function, a memory receiving an address supplied from said microprocessor to output data designated by the received address, an address decoder receiving and decoding said address supplied from said microprocessor, and a memory control circuit receiving an output of said address decoder and control signals from said microprocessor, for controlling said memory. The system is configured to generate a burst mode transfer period designating signal indicating a period of a burst mode transfer, so that a synchronous burst mode transfer is performed in accordance with the period of the burst mode transfer designated by said burst mode transfer period designating signal, so as to cause said microcomputer to fetch data transferred from said memory by the synchronous burst mode transfer.