Abstract: A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a self-test module. The self-test module includes a pattern generator producing write data having a predetermined pattern, and a flip-flop having a data input receiving the write data. A clock input of the flip-flop receives an internal clock signal from a delay line that receives a variable frequency clock generator. Read data are coupled from the memory devices and their pattern compared to the write data pattern. The delay of the delay line and frequency of the clock signal can be varied to test the speed margins of the memory devices.

Abstract: The number of S-FFs in a scan-path is decreased by half and a test time needed is decreased. An I/O terminal 1A is connected to a scan-path 31-3m and a combination circuit 2 via a selector 5A and an output of the scan-path 31-3m is connected to an I/O terminal 1B via a selector 6A and a tri-state buffer 7A. The I/O terminal 1B is connected to a scan-path 3m+1-3n and to the combination circuit 2 via a selector 5B and the output of the scan-path 3m+1-3n is connected to the I/O terminal 1A via a selector 6B and tri-state buffer 7B. When testing, the tri-state buffers are turned off and test-data are supplied by connecting the I/O terminal 1A, 1B to the scan-path 31-3m, 3m+1-3n respectively. Thereafter, output signals of the combination circuit is applied to each S-FF 3, and the test data are read out from the I/O terminal 1A, 1B by turning on the each tri-state buffer 7A, 7B.

Abstract: A memory device and a method of controlling an input signal of the memory device. In the method of controlling an input signal according to test modes, it is determined whether the input signal is in a first test mode or a second test mode. If the memory device is in the first test mode, in response to a control signal, an input signal is received through input pins. In response to a mode signal, the input signal is separated into data and an address. The separated data and address is applied to the core of a memory device. If the memory device is in the second test mode, an input signal is received through input pins and inverting input pins. In response to a mode signal, an address is separated from the input signal received through the input pins and the data is separated from the input signal received through the inverting input pins. The separated data and address are applied to the core of a memory device.

Abstract: A testing device for a semiconductor storage device suppresses the increase in the circuit size, provides for facilitated accommodation to a test with frequent changes in the test pattern, and improves testability of the semiconductor storage device. A plurality of holding circuits are provided holding write data for memory cells of a memory cell array. (Original) The write data from the holding circuits are written in the memory cells of the selected address. A plurality of comparators are supplied with data read out from the memory cells and with data held by the holding circuits as expectation data to compare the readout data and the expectation data. The non-inverted or inverted value of the write data held by the holding circuits is output as the write data to the memory cells and as expectation data to the comparators depending on the value of the inversion control signal.

Abstract: The present invention is directed to an improved method, system and apparatus for self-testing an electronic device. A scan latch used in a multi-cycle bus is uniquely operated to generate signal transitions consistent with the normal operating speed of the device. This occurs even when a normal signal transition would not otherwise occur since the multi-cycle bus normally requires a plurality of clock pulses to create such signal transition. The logical states of master and slave clocks associated with test scan logic are used to automatically cause the output of a scan latch to invert its output or switch from its previous state at each rising edge of the slave clock that is not preceded by a master or scan clock.

Abstract: Methods, systems, and apparatuses are provided to emulate bus transactions for a device under test (DUT). Test data is sent from a testing device to a cache of a DUT. When data needs to be read or written to locations outside of the cache (e.g., bus action is needed), a pseudo bus agent (PBA) is activated. The PBA emulates the reads or writes and provides pseudo data back to the cache. In some embodiments, results of bus transactions are compressed to form a bus signature that is provided back to the testing device for validation.

Abstract: A system and method are disclosed for error correction in a programmable logic device (PLD). A frame circuit retrieves data from each column of configuration memory of the PLD, and a check memory stores of a plurality of check words. A buffer circuit is coupled to the check memory and to the frame circuit. The buffer circuit assembles blocks of data from data retrieved by the frame circuit and from corresponding check words in the check memory. A plurality of storage elements are provided for storage of status information. A check circuit is coupled to the storage elements and to the buffer circuit. Each block is checked by the check circuit using an error correcting code, and data indicating detected errors is stored in the storage elements.

Abstract: An accelerated test method evaluates, under accelerated conditions (a temperature T2 and a voltage V2), an endurance characteristic of a ferroelectric memory device having a capacitor element including a ferroelectric film under actual operating conditions (a temperature T1 and a voltage V1). An acceleration factor (K) required to evaluate the endurance characteristic is derived by using an expression: logK=A(1/V1?1/V2)+B(1/V1T1?1/V2T2) (where each of A and B is a constant).