Patents Examined by Sarah L Ell
  • Patent number: 12165983
    Abstract: An integrated circuit assembly may be formed comprising a stepped electronic substrate having a first surface and an opposing second surface, wherein the first surface comprises a first surface portion or lower step and a second surface portion or upper step. At least one integrated circuit device may be electrically attached to the first surface portion of the first surface of the stepped electronic substrate and an anisotropic conductive layer on the second surface portion of the first surface of stepped electronic substrate. The anisotropic conductive layer may be used to electrically couple the integrated circuit assembly with an additional integrated circuit assembly.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: December 10, 2024
    Assignee: Intel Corporation
    Inventors: Eleanor Patricia Paras Rabadam, Maria Angela Damille Ramiso
  • Patent number: 12167593
    Abstract: There are provided a semiconductor memory device and a method of manufacturing a semiconductor memory device. The semiconductor memory device includes a conductive pattern, an etch stop layer on the conductive pattern, a conductive bonding pattern including a contact portion connected to the conductive pattern, and a pad portion extending from the contact portion, a first dielectric layer disposed on the etch stop layer and spaced apart from the conductive bonding pattern, and a second dielectric layer including a first portion surrounding a sidewall of the contact portion of the conductive bonding pattern between the pad portion of the conductive bonding pattern and the etch stop layer, and a second portion extending from the first portion to cover an upper surface of the first dielectric layer.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: December 10, 2024
    Assignee: SK hynix Inc.
    Inventors: Jae Young Oh, Nam Jae Lee
  • Patent number: 12148802
    Abstract: A driver circuit for a three-dimensional (3D) memory device has a field management structure electrically coupled to a gate conductor. The field management structure causes an electric field peak in a vertical channel of the 3D memory device when a voltage differential exists between the source conductor and the drain conductor and the gate conductor is not biased. The electrical field peak can adjust the electrical response of the driver circuit, enabling the circuit to have a higher breakdown threshold voltage and improved drive current. Thus, the driver circuit can enable a scalable vertical string driver that is above the memory array instead of under the memory array circuitry.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: November 19, 2024
    Assignee: Intel NDTM US LLC
    Inventors: Dong Ji, Guangyu Huang, Deepak Thimmegowda
  • Patent number: 12127446
    Abstract: A display device includes a substrate including a plurality of sub-pixels, a first buffer layer on the substrate, an etch stopper on the first buffer layer, a second buffer layer covering the first buffer layer, and a first transistor on the second buffer layer. The first transistor includes a source electrode and a drain electrode overlapping the etch stopper. The etch stopper includes a hole in which at least one of the source electrode and the drain electrode is disposed. The etch stopper is spaced apart from the source electrode and the drain electrode. Therefore, it is possible to prevent moisture and impurities from penetrating into a display device by protecting a buffer layer.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: October 22, 2024
    Assignee: LG Display Co., Ltd.
    Inventors: SeongPil Cho, JunSeuk Lee, YongBin Kang, HeeJin Jung, Jangdae Kim, Dongyup Kim, WonHo Son, Chanho Kim
  • Patent number: 12068343
    Abstract: An image sensing device is provided to include a plurality of unit pixel regions arranged in a first direction and a second direction, a first device isolation region structured to isolate the plurality of unit pixel regions from each other, a plurality of photoelectric conversion regions in the substrate to form a plurality of imaging pixels structured to generate photocharges, a plurality of second device isolation regions configured to define active regions of the plurality of imaging pixels, a plurality of floating diffusion regions formed in a first active region to store the photocharges, and a plurality of transfer gates structured to transmit the photocharges. The floating diffusion region is located contiguous to the transfer gate in the first direction and the second direction and is structured to surround a plurality of side surfaces of a corresponding transfer gate.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: August 20, 2024
    Assignee: SK HYNIX INC.
    Inventors: Jong Hwan Shin, Seung Hoon Sa