Abstract: A system and method to verify software includes a debugger setting a breakpoint in the software. The breakpoint indicates a point at which to pause or stop execution of the software. The method also includes setting one or more anchor points associated with the breakpoint. Each of the one or more anchor points represents another point in the software that must be executed prior to pausing or stopping the execution of the software at the breakpoint.

Abstract: Techniques described herein generally relate to a task management system for a chip multiprocessor having multiple processor cores. The task management system tracks the changing instruction set capabilities of each processor core and selects processor cores for use based on the tracked capabilities. In this way, a processor core with one or more failed processing elements can still be used effectively, since the processor core may be selected to process instruction sets that do not use the failed processing elements.

Abstract: A prioritized error detection schedule may be generated using computer-aided-design (CAD) tools that receive specifications of critical regions within an array of configuration random access memory (CRAM) cells on an integrated circuit. Each of the specified critical regions may be provided a respective criticality weight. The proportion of indices in a prioritized error detection schedule that prescribe error detection for a given critical region may be based on the criticality weight of the given critical region. A prioritized error detection schedule may prescribe more frequent error correction for critical regions with higher criticality weights relative to critical regions with lower criticality weights. Addressing circuitry on the integrated circuit may be used to read out data from critical regions of CRAM in the order prescribed by the prioritized error detection schedule and check the read out CRAM data for errors.

Abstract: A method for correcting bit defects in an STT-MRAM memory is disclosed. The method comprises executing a read before write operation in the STT-MRAM memory, wherein the STT-MRAM memory comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. The read before write operation comprises reading a codeword and mapping defective bits in the codeword. Further, the method comprises replacing the defective bits in the codeword with a corresponding redundant bit and executing a write operation with corresponding redundant bits in place of the defective bits.

Abstract: A technique for managing RAID storage in a data storage system provides a mapping subsystem and a RAID subsystem and employs the mapping subsystem to direct repair operations on damaged RAID stripes. The mapping subsystem stores metadata that provides information about data stored in the RAID subsystem and locations of that data on RAID stripes. In response to detection of a damaged RAID stripe, the mapping subsystem selectively determines, based on the metadata, whether to perform repair operations or to avoid repair operations. As many repair operations can safely be avoided, the disclosed technique has the effect of reducing unnecessary processing in the data storage system. When the RAID subsystem includes flash drives, the technique also reduces write amplification, thus preserving flash drives which might otherwise be subject to premature wear.

Abstract: Techniques for on-demand remote diagnostics for hardware component/device failure and disk drive data recovery using embedded media are described. In one example embodiment, a hardware device failure event alert along with a unique ID and a hardware device configuration fingerprint is sent upon detecting a hardware component failure event associated with the hardware device in a datacenter to an image management framework. A recovery image associated with the hardware device failure event is then obtained using the unique ID and the hardware device configuration fingerprint. The recovery image is then stored in an embedded storage media associated with the failed hardware device. The embedded storage media is then configured as a bootable hardware device. The hardware component failure is then diagnosed using the stored recovery image and the bootable hardware device upon hardware device boot-up. Recovering from the hardware device failure based on diagnosing the hardware component failure.

Abstract: Techniques that facilitate re-hosting a subset of a serverless application are provided. In one example, a system includes an interface component, a rewriter component and a broker component. The interface component receives identifier data from a computing device that identifies a portion of a serverless application to be re-hosted by the computing device. The computing device is in communication with the serverless computing system via a network device. The rewriter component rewrites the serverless application to allow the first portion of the serverless application to be executed by the computing device and another portion of the serverless application to be executed by the serverless computing system. The interface component re-routes the first portion of the serverless application to the computing device to facilitate a debugging session for the first portion of the serverless application that is performed by the computing device.

Abstract: The present disclosure includes apparatuses comprising replaceable memory. An example apparatus may include a controller and a memory package coupled to the controller and including a plurality of memory dies. At least one of the memory package and the controller may be a replaceable unit that is removable from the apparatus and replaceable with a different replaceable unit while maintaining operation of the apparatus.

Abstract: A method for correcting bit defects in a memory array is disclosed. The method comprises determining, during a characterization stage, a resistance distribution for the memory array by classifying a state of each bit-cell in the memory array, wherein the memory array comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. Further, the method comprises determining bit-cells in the resistance distribution that are ambiguous, wherein ambiguous bit-cells have ambiguous resistances between being high or low bits. Subsequently, the method comprises forcing the ambiguous bit-cells to short circuits and replacing each short-circuited ambiguous bit-cell with a corresponding redundant bit from an associated codeword.

Abstract: In one example, mapping information corresponding to a container running on a private data center may be generated in a public cloud by a processor-based disaster recovery manager. Further, volume data associated with the container may be synchronized to the public cloud based on the mapping information by the disaster recovery manager. Furthermore, a failure of the container running on the private data center may be determined by the disaster recovery manager. In response to the failure of the container running on the private data center, the container may be deployed in the public cloud using the synchronized volume data and the mapping information by the disaster recovery manager.

Abstract: According to one embodiment, a memory system includes a non-volatile first memory, a second memory, a battery, a first processor, and a second processor. The first processor is configured to execute fault diagnosis on the battery by discharging energy stored in the battery. The second processor is configured to write data cached in the second memory into the first memory and reduce an upper limit of the amount of data to be cached when executing the fault diagnosis than the upper limit of the amount of data to be cached when not executing the fault diagnosis.

Abstract: Embodiments include systems, methods, and computer program products for on-demand error detection and correction of registers in a processor. One method includes detecting, before a first instruction is dispatched to an issue queue in the processor, an error in data, associated with the first instruction, stored in an entry of a register file in the processor. The method also includes, after detecting the error, halting the dispatch of the first instruction to the issue queue, and determining whether the entry of the register file has completed. The method further includes determining whether to perform error correction on the register file based on the determination of whether the entry of the register file has completed.

Abstract: Disclosed are various embodiments for a distributed code tracing system that provides code tracing as a service in a multi-tenant computing environment. In one embodiment, a code trace is received that is associated with a request submitted to a particular application hosted in a computing environment, where multiple applications are hosted in the computing environment. The code trace documents calls to multiple component services of the particular application in order to respond to the request. The code trace is compressed using time-based compression. The compressed code trace is then stored in a data store that is indexed by a unique identifier of the request.

Abstract: Exemplary methods, apparatuses, and systems include a recovery manager receiving selection of a storage profile to be protected. The storage profile is an abstraction of a set of one or more logical storage devices that are treated as a single entity based upon common storage capabilities. In response to the selection of the storage profile to be protected, a set of virtual datacenter entities associated with the storage profile is added to a disaster recovery plan to automate a failover of the set of virtual datacenter entities from a protection site to a recovery site. The set of one or more virtual datacenter entities includes one or more virtual machines, one or more logical storage devices, or a combination of virtual machines and logical storage devices. The set of virtual datacenter entities is expandable and interchangeable with other virtual datacenter entities.

Abstract: A method for correcting bit defects in a memory array is disclosed. The method comprises determining a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for all bits comprising the memory array, wherein the margin area is a bandwidth of bit-cell resistances centered around a reference point associated with a sense amplifier, wherein the bit-cell resistances of memory bit-cells associated with the margin area are ambiguous. The method further comprises forcing the bit-cell resistances of memory bit-cells associated with the margin area to short circuits. Finally, the method comprises replacing each short-circuited memory bit-cell with a corresponding redundant bit in the codeword associated with the short-circuited memory bit-cell.

Abstract: Systems and methods are disclosed for a journal for a storage class memory device. The storage class memory device may execute an access command for a first page in the storage class memory device. The storage class memory device may also determine whether a failure occurred while executing the access command. The storage class memory device may create an entry in a journal for the storage class memory device if a failure occurred while executing the access command. The storage class memory device may refrain from creating the entry if a failure does not occur while executing the access command.

Abstract: The example embodiments are directed to an automated cloud platform certification process. In one example, the method includes receiving a request for adding an application to the cloud platform, executing the application and performing an automated certification process based on the executed application. According to various embodiments, the automated certification process may include verifying an output of the executed application, verifying an impact of the executed application on the cloud platform is below a predetermined threshold, and verifying the executed application satisfies applicable coding guidelines. The application may be stored or launched on the cloud platform following successful certification.

Abstract: An example method of providing a crash dump file upon a crash of a guest OS includes receiving, by a hypervisor, a notification that a guest OS running on a virtual machine has crashed. The notification is from the guest OS, and the virtual machine and the hypervisor run on a host machine. The method also includes in response to receiving the notification, writing, by the hypervisor, a crash dump file associated with the guest OS crash to a host file system of the host machine.

Abstract: In one aspect, a system for automatic application repair by a network device agent in a monitored environment includes a processor; a memory; and one or more modules stored in the memory and executable by a processor to perform operations including: capture network device application data for a monitored application, the network device performing a function other than computing, analyze the captured data to detect a performance issue, identify a remedy associated with training data that corresponds to the captured data, and automatically applying the remedy to the network device.

Abstract: A computing system can include a processor and a persistent main memory including a fault tolerance capability. The computing system can also include a memory controller to store data in the persistent main memory and create redundant data. The memory controller can also store the redundant data remotely with respect to the persistent main memory. The memory controller can further access the redundant data during failure of the persistent main memory.