Abstract: A memory control device for controlling a random access memory provides with an arbiter for generating write start and read start signals in response to WRITE and READ commands which are obtained by frequency-dividing writing and reading clock signals, respectively and a memory control circuit comprised of first and second delay circuits for delaying the write start and read start signals by predetermined times, respectively, and first and second RS flip-flop circuits for generating write and read control signals in response to the write start and read start signals, respectively, which are reset by reset signals output from the first and second delay circuits, respectively.

Abstract: A power-on reset circuit including a constant voltage circuit element in which a voltage drop is limited to within a fixed value, a transistor to which a source voltage is applied from the constant voltage circuit element and a gate voltage is applied from a power source voltage to be monitored, a current path forming element, connected to the drain of the transistor, fed with current from a power source voltage, and an invertor an input terminal of which is connected to a node of the current path forming element and the transistor.

Abstract: A power switch responsive to drive signals developed by a signal source includes driver and driven transistors connected in a Darlington configuration and a further transistor having a control electrode and first and second main current path electrodes wherein the first main current path electrode of the further transistor is coupled to first main current path electrodes of the driver and driven transistors, the second main current path electrode ofo the further transistor is coupled to a control electrode of one of the driver and driven transistors and the control electrode of the further transistor receives the drive signals. The power switch is maintained in a saturated state over a wide range of load current magnitudes.