Abstract: A semiconductor device includes a semiconductor chip attached to a lead frame with recesses on the rear surface of the semiconductor chip opposite the lead frame. These recesses increase the heat radiation area of the semiconductor chip. In a method of producing a semiconductor device, the height of a cavity between upper and lower dies is smaller than the height of the semiconductor chip including bump electrodes. During a molding process, the bump electrodes contact the upper die or a dam surrounding the bump electrodes so that no thin burrs are produced on the surfaces of the bump electrodes in the molding process.

Abstract: A method of removing ceramic material, such as for example a ceramic core, from a metallic cast or other component involves contacting the metallic cast component and a caustic ceramic leaching medium at elevated temperature for a time effective to substantially remove the ceramic material from the component and providing an oxygen getter in the caustic ceramic leaching medium in an amount effective to avoid deleterious surface corrosion of the component while the ceramic material is being removed therefrom.

Abstract: A process for providing a temporary, non-intrusive electrical connection to bond pads of a semiconductor die permitting test and burn-in of bare die. Modified tape automated bonding (TAB) techniques are used with gold bumped die bond pads for providing known good die (KGD). After test and burn-in, the temporary connection to the die is removed without the need to reform the gold bumps prior to use in a multichip module. Gold inner leads of a TAB tape are diffusion bonded to gold bumps wherein the bonding is sufficient for providing electrical connection during the testing and burn-in of the die yet sufficiently weak for removal of the leads from the die after testing and burn-in. The process provides the KGD necessary for acceptable first assembly yields and long term reliability of multichip modules (MCM). Bare die with gold bumped, sealed bond pads are provided simplifying interconnection during testing and ultimate module use.

Abstract: A method of bonding an integrated circuit die to a heat sink by first providing a lead frame that has a die paddle portion having a top surface, a bottom surface, and at least one aperture therethrough, positioning a heat sink abutting the bottom surface of the die paddle portion, and then pressing an integrated circuit die against the top surface of the die paddle portion with an adhesive material sandwiched therein between such that the adhesive flows through at least one aperture in the die paddle portion to bond the integrated circuit die and the heat sink together.

Abstract: An electrochemical sensor assembly which allows a solution to make contact with an active sensing area of a sensor, while constraining the solution such that the fluid does not contact the sensor electronics and a method for fabricating such a sensor assembly. A sensor assembly is fabricated in accordance with a simple process, including: fabricating a master pattern which matches the external profile of an epoxy shell which will encapsulate a substrate upon which the sensors are mounted; forming a flexible tool (or mold) which conforms to the general profile of the master pattern; placing sensors together with any other desired electronic circuitry on a substrate (such as a printed circuit board or a ceramic pad to form a "hybrid"); pressing a number of electrical contact points on the hybrid and the active sensing area of each sensor on the substrate into contact with flexible protrusions of the flexible tool; and potting the hybrid.

Abstract: A method for forming solder ball contacts on a Ball Grid Array (BGA) is described. The solder balls are formed by squeegeeing solder paste through apertures in a fixture into contact with pads on a substrate, and heating the fixture, paste and substrate to reflow the solder paste into solder balls that attach to the pads and are detached from the fixture. After cooling, the fixture is readily separated from the substrate while leaving the solder balls in positive (conductive) contact with contact pads on the substrate.

Abstract: A polysilicon resistor (40) includes a field oxide layer (12) and a polysilicon layer (20) that covers a portion of field oxide layer (12). The polysilicon layer (20) possesses a predetermined electrical resistance value. Nitride/oxide stack (42) covers a predetermined portion of the polysilicon layer (20) and forms at least one exposed location of polysilicon layer (20) on which not to implant a dopant to achieve a predetermined resistance value. Silicide layer (34) covers exposed location.

Abstract: A metal system that can be adjusted to obtain higher alloying temperatures in AlInAs/GaInAs heterostuctures is disclosed. Increasing the thickness of a Ag layer in the metal system facilitates higher alloying temperatures and, consequently, improved ohmic contact reliability. The system is particularly directed to use in Al.sub.x In.sub.1-x As/Ga.sub.0.47 In.sub.0.53 As with 0.48<x<1 power HFETs.

Abstract: A method of producing a semiconductor device is disclosed and includes steps of temporarily connecting inner leads or lands provided on a film carrier tape and electrode pads provided on an IC chip at the same time by low-temperature gang bonding, and then bonding them by point bonding. The method enhances the reliable production of a semiconductor device by reducing the influence of localized load and temperature ascribable to the short accuracy of the gang bonding jig as well as the influence of the deformation of a film carrier tape due to heat applied during point bonding.

Abstract: A laser processing process which includes laser annealing a silicon film 2 .mu.m or less in thickness by irradiating a laser beam 400 nm or less in wavelength and being operated in pulsed mode with a pulse width of 50 nsec or more and preferably, 100 nsec or more. The invention further relates to a laser processing apparatus which includes a laser generation device and a stage for mounting thereon a sample provide separately from said device, to thereby prevent transfer of vibration attributed to the movement of the stage to the laser generation device and the optical system. A stable laser beam can be obtained to thereby improve productivity.

Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. TAB processes are disclosed for cutting, bending and bonding inner and outer portions of selected signal layer traces to respective inner and outer edge portions of the additional conductive layer(s), including a two-stage process of (1) first cutting, bending and tacking the selected traces to the additional layer(s), and then (2) repositioning a bonding tool and securely bonding the selected traces to the additional layer(s). A tool (die pedestal) for aiding in the assembly process is also disclosed.

Abstract: A miniaturized electronic imaging chip has stratified layers wherein a base silicon layer has a peripheral edge defining an area and a thickness which allows passage therethrough of most UV, visible and IR light. A pixel layer is formed on the back side of this first silicon layer. At least one interconnect layer is bonded to the pixel layer. Electric leads are bump bonded to the bonding pads on the outermost interconnect layer and extend away from it within the area for attachment to means for sensing electrical signals generated by an image projected onto the pixel layer through the silicon layer. Preferably, the leads are perpendicular to the chip. A unique method of manufacturing the miniaturized electronic imaging chip from a standard CCD comprises the steps of shaving a silicon layer, having a peripheral edge defining a second area which is smaller than the first area, on the back side of the standard CCD to a thickness which allows passage of a light image therethrough.

Abstract: A PMOS device is provided having a diffusion barrier placed within the polysilicon gate. The diffusion barrier is purposefully deposited to a concentration peak density within the gate which is deeper than subsequently placed impurity dopant. The barrier comprises germanium atoms placed in fairly close proximity to one another within the gate conductor, and the impurity dopant comprises an ionized compound of BF.sub.2 subsequently placed as boron within the gate and source/drain region, at least a majority and preferably greater than eighty percent of which are placed shallower within the gate than the germanium atoms. The barrier region substantially prevents or retards penetration of boron atoms through the gate oxide and into the channel region. Thus, the barrier helps prevent change in channel concentration and problems associated with boron penetration such as flatband voltage (Vfb) and threshold voltage (Vth) shift.

Abstract: A method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a conductive film on an insulating film, forming growth nucleuses containing any of elements in group IIIb, group IVb, group Vb and group VIIb that does not constitute the conductive film and the insulating film on the surface of the conductive film, and growing a semiconductor selectively on growth nucleuses.

Abstract: A method of fabricating high-voltage diode device on a silicon substrate which includes a first region and a second region is provided. The first and second regions having a first contact and a second contact area respectively. First, a first protective layer is formed on the first and second contact areas. A second protective layer is formed on the first protective layer and a portion of the first region adjacent to the first contact area. Next. Halogen ions are implanted into the first and second regions by using the second protective layer as a mask. The second protective layer is removed to expose unimplanted portion of the first region. Then, the first and second regions are oxidized to form a field oxide layer by using the first protective layer as a mask, wherein the unimplanted portion of the first region has a relatively lower oxidation rate and thereby a stepped part of the field oxide layer is formed over the first region.

Abstract: A method of manufacturing bump electrodes with a larger top surface area than bottom surface area is disclosed. First, an organic layer is deposited. Then holes and grooves partially surrounding the holes are formed in the organic layer. Next, heat is applied to the organic film, causing the organic film to shrink. This causes the openings to expand at the top away from the grooves partially surrounding the holes. Metallic bumps are then deposited within the holes.

Abstract: A polysilicon ground plane is formed over dielectric layers and under a suspended, movable mass in a surface micromachined device. The process includes steps of forming a diffused region in a substrate, forming the dielectric layers over the substrate, forming the ground plane over dielectric layers, and forming a body having a suspended mass, a first anchor extending from the mass down to the diffused region, and a second anchor extending from the mass down to the ground plane. The two anchors are formed simultaneously. The ground plane, which can be formed with only three additional steps over prior processes, serves as a ground plane to control changes and also as a local interconnect.

Abstract: A method for forming contact holes, capable of achieving an increased tolerance in design rule for formation of contact holes by: forming an insulating film over a semiconductor substrate; coating a positive photoresist film over the insulating film; primarily exposing the photoresist film to a light using a first exposure mask having windows adapted to allow portions of the insulating film corresponding to a part of contact holes to be exposed to the light, the part of contact holes having contact holes arranged diagonally to each other; secondarily exposing the photoresist film to the light using a second exposure mask having windows arranged diagonally to each other and not overlapped with those of the first exposure mask; removing the light-exposed portions of the photoresist film to form a photoresist film pattern for exposing portions of the insulating film respectively corresponding to the contact holes; and forming the contact holes using the photoresist film pattern as a mask.

Abstract: The present invention discloses a structure of a transistor in a semiconductor device and a method of manufacturing the same. The present invention manufactures a high voltage transistor by etching a silicon substrate to a depth deeper than that of the field oxide film by a self-aligned wet etching process using the field oxide film as a mask and, thereafter, by forming the first gate electrode which electrically switches ON and OFF between the source region and the drain region by using a gate electrode mask and simultaneously forming a second gate electrode to prevent a junction breakdown below the bird's beak of the field oxide film. Accordingly, the present invention can improve the degree of integration of the device by forming a gate electrode to prevent a junction breakdown below the bird's beak of the field oxide film.

Abstract: A process for fabricating a thin-film structure using a transparent substrate is disclosed. A first structure, such as a ring having a central pillar, is formed of a conductive material on a surface of the substrate. A photoresist material pillar is formed on top of the conductive material central pillar by exposure through the transparent material. Such structures are useful as mandrel structures in the forming of precision thin-film components such as nozzle plates, mesh filter screens, and the like, for ink-jet pens.