Abstract: A Managed Site (10), a logical network entity, is composed of a number of Sub Sites (20) in a one to many relationship. A Sub Site (20) is a logical component, which is composed of a number of Engines (30). Nodes (40) similarly relates to their Engine (30) in a many to one relationship. A Node (40) is a collection of Managed Elements (ME's) (50) (while being an ME (50) itself), which represent network state information. The subsite (20) consists of the engine (30) connected to server nodes (40). One or more clients (110) are connected to the management engine (30) and access management engine (30) information relating to managed elements (50) including nodes (40). The connected manager engines may communicate with one another so that, for example, in the event of a failure, one of the manager engines remaining on line commences monitoring of manage elements assigned to the failed manager engine.

Abstract: The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction for a “block” of instruction memory. The block of instruction memory is represented by a block entry in the fetch-block branch target buffer. The block entry represents one recorded control-transfer instruction (such as a branch instruction) and a set of sequentially preceding instructions, up to a fixed maximum length N. Indexing into the fetch-block branch target buffer yields an answer whether the block entry represents memory that contains a previously executed a control-transfer instruction, a length value representing the amount of memory that contains the instructions represented by the block, and an indicator for the type of control-transfer instruction that terminates the block, its target and outcome.

Abstract: A method and system is provided for migrating processes from one virtual machine to another on a network. To migrate the external state of a process, the process may use a network service connection system or a compact network service connection system for accessing resources external to the virtual machine. A process may be migratable separately from other processes. A process may have an in-memory heap used for the execution of the process, a virtual heap that may include the entire heap of the process including at least a portion of the runtime environment, and a persistent heap where the virtual heap may be checkpointed. In one embodiment, the virtual heap may serve as the persistent heap. In another embodiment, the virtual heap may be checkpointed to a separate, distinct persistent heap. The combination of the in-memory heap, the virtual heap, and the persistent store may be referred to as a virtual persistent heap.

Abstract: An OP-N connection is mapped through a communications network between first and second end-nodes via at least one intermediate node. The integrity and validity of the OP-N connection can be determined independently of SONET/SDH lines, sections or paths mapped through the network, and potentially utilizing bandwidth of the OP-N connection. Validation of the OP-N connection can be accomplished by inserting performance monitor (PM) information into a data signal at the first end-node. The PM information is inserted into the synchronous payload envelope (SPE) of a SONET/SDH data signal. At each intermediate node between the first and second end-nodes, the PM information may be extracted, examined and/or augmented or simply pointer processed before the data signal is forwarded. At the second end-point, the PM information is extracted and examined. Multiple levels of OP-N connections are supported, with each level being provided with a respective set of PM information carried in the SPE.

Abstract: An apparatus is described comprising a signal indicative of which of a plurality of data structures stored in a queue desire to issue from the queue. The apparatus also has a content addressable memory having a plurality of cells, where each of the cells is configured to store one of the data structures. The apparatus also has an output from at least one of the cells that is indicative of whether the data structure within the at least one of the cells has issued from the queue. The apparatus also has an input to the at least one of the cells coupled to the signal.

Abstract: A system and method with which competing resource requests can be processed in accordance with a predefined priority list of the different requesting processes, without necessitating a real-time operating system or a complete handshake protocol mechanism for processing the messages between an assignment device and requesting devices or processes. The methods and systems can be used in service-feature servers of switching devices which are preferably connected via a CTI interface to the switching device.

Abstract: Techniques for handling objects in a network cache are described. A cost function value is calculated for each of a plurality of data objects. The cost function value relates to at least one metric relating to a total time required to download a corresponding one of the plurality of data objects. Each of the plurality of data objects are handled by the network cache according to its cost function value.

Abstract: A global sign-on mechanism (GSO) is implemented. The mechanism provides a GSO system and method for a networked data processing system within an open architecture framework. The system and method are constructed on a Lightweight Directory Access Protocol (LDAP) framework by defining a set of data structures, the GSO LDAP schema. GSO functionality is effected using protocol operations on the LDAP object and attribute instances as defined in accordance with the GSO schema.

Abstract: A method for remotely accessing at least one of at least one CAN node arrangement of a CAN bus arrangement associated with the vehicle during vehicle operation, the CAN bus arrangement being associated with a CAN gateway arrangement for coupling to an external network, inn which the method includes the steps of communicating an initialization control message from the CAN gateway arrangement to the at least one CAN node arrangement using the CAN bus arrangement, the initialization control message including a CAN node arrangement identifier code, comparing the CAN node arrangement identifier code with a unique CAN node arrangement identifier code stored at each of the at least one CAN node arrangement for determining a selected CAN node arrangement based on the CAN node arrangement identifier code and the unique CAN node arrangement identifier code, processing the initialization control message using the selected CAN node arrangement, communicating a data addressing message from the CAN gateway arrangement to t

Abstract: One embodiment of the present invention provides a system that facilitates forwarding fragments of a packet received from a source node to a destination node, wherein the destination node is determined based upon information within a first fragment of the packet. The system operates by receiving at least one fragment of the packet at an interface node from the source node. The system uses a packet identifier from the fragment to look up an entry for the packet within a packet forwarding data structure. If this entry specifies the destination node, the system forwards the fragment to the destination node. If the entry does not specify the destination node, and if the fragment is not the first fragment of the packet, the system links the fragment into the entry for the packet within the packet forwarding data structure, so that the fragment can be forwarded to the destination node when the destination node later becomes known.

Abstract: The present invention deals with the problem with packet based services consuming considerable bandwidth over links with shortage of bandwidth. The object of the present invention is to reduce the amount of information when transferring a signalling message and thus save bandwidth. After receiving a signalling message in a first node the signalling message is identified. The signalling message is replaced by an indicator, under usage of information from the identification, which indicator is transferred to a second node. The second node restores the signalling message using the indicator.

Abstract: A multi-protocol switching system of the invention has a plurality of line interfaces that has an input section for inputting data from a network, a forwarding table, a determination section for determining a destination or the input data, a packet generating section for generating a packet, when the destination determined is a protocol processor, by adding a processor identifier of the protocol processor and a port number to which the multi-protocol processing device is connected to the input data, and an output section for outputting the packet through the port to a switch. Also it has one or more multi-protocol processing devices that has a switch interface, a plurality of protocol processors which are provided corresponding to the kind of protocol and each of which has a processor identifier defined in the multi-protocol processing device, and a processor selecting section.

Abstract: An instruction processing apparatus using a microprogram instruction which implements re-reading operation. The instruction execution apparatus is provided with a queue stack, a unit halting requests for reading subsequent instructions at the instruction of a microprogram, and a unit releasing this halt. Further, by instruction the reading of the subsequent instructions using the microprogram control information, it becomes possible to simultaneously execute the microprogram and instruction re-reading processing. Because the Program Status Word Instruction Address (PSWIAR) of the load control (LCTL) plus the instruction length of the PSWIAR makes an instruction fetch address of the LCTL, the hardware of the instruction re-read address production circuit (which is a part of the instruction processing circuit) can be used.

Abstract: A method and apparatus that utilizes a simple test and flush mechanism to implement branch instructions of one Instruction Set Architecture (ISA) using instructions of another ISA is described. During the decoding and sequencing of microinstructions to implement a branch instruction, a fix-up address, which represents the remedial branch target in the event of a mispredicted target or branch condition, is determined and stored. A test condition is set to determine if the prediction or the branch condition was correct. When the test condition fails, the instruction execution pipeline is immediately flushed to avoid executing any instruction remaining in the pipeline following the branch instructions. The flushing of the pipeline signals the instruction fetch control mechanism to redirect the instruction flow to the instruction corresponding to the fix-up address.

Abstract: A system, method and computer program product that pre-caches or downloads information from internet sites that the system expects the user to request. The system schedules the pre-caching to occur at the most appropriate time of day in order to increase the likelihood that the most recent information is provided to the user in a timely manner. Actual usage is monitored to adjust to user-changing habits, conserve resources at both the server and client ends, and prioritize information against interrupted downloads and exhausted or limited cache or memory space. For users that use the telephone to dial-in to the internet, the system and method pre-caches content in a manner which decreases the likelihood that the pre-caching process will interfere with the user's use of the telephone for other purposes.

Abstract: Graphics enabled applications run on a text-based host server by allowing a client application running at a workstation to inform the server of this session (1) that it, the client application, is graphics capable and (2) the IP address and port(s) it is waiting on; and then by having the server set capability indicia, such as rwt attributes, in the operating system for this session to indicate the (1) the client is graphics enabled, (2) the IP address and port(s) it is waiting on, (3) optionally, the path to an application to be automatically launched.

Abstract: An electronic mail system for efficiently transmitting mail data according to a change of the transmission condition of the wireless transmission path is disclosed. The system comprises a mail sender including a mail receiving unit, storage device, mail sending unit, command interpreting section, and mail order rearranging section, and a mail receiver including a mail receiving unit, a receiving condition monitoring section, and a command issuing section. The mail receiving unit monitors the condition of receiving mail data at predetermined intervals, and generates a detection signal when the receiving condition changes. According to the detection signal, the mail receiver sends a command ordering the rearrangement of the mail data. The mail sender receives the command, and rearranges the mail data stored in the storage device.

Abstract: A method and apparatus for enabling the correct architectural sequencing of fetched instructions prior to allowing the instructions to complete in the processor pipeline to reduce the occurrence of pipeline breaks. A branch processing unit (BPU) is designed to perform sequence checks for the addresses of all instructions fetched into the pipeline (i.e., both in-line and branch instructions) by the instruction fetch unit (IFU). A first instruction is fetched. The address of the next instruction in the architectural sequence is computed and stored within the BPU. The next instruction is fetched and its address is compared to the next instruction address stored in BPU to determine if it is the correct address. If the next instruction address matches that of the architectural sequence, the instruction is permitted to “live” (i.e., continue through to completion). When the address does not match, the instruction is killed (i.e., not allowed to complete) and a new instruction is fetched by the IFU.

Abstract: An IP packet reassembly engine provides high-speed and efficient reassembly of IP fragments received at an intermediate station in a computer network. The IP packet reassembly engine comprises a main controller logic circuit configured to “speed-up” re-assembly of original packets from IP fragments stored in a frame buffer at multi-gigabit per second rates. To that end, the reassembly engine further includes a content addressable memory having a plurality of entries for maintaining status information for each received fragment and for each original packet being reassembled from the fragments.

Abstract: A pipelined processor and method are disclosed for speculatively determining dependencies. The processor processes a plurality of instructions in order. A speculative detection circuit which takes multiple clock cycles to operate determines whether a dependency exists. The speculative detection circuit inserts a single-cycle pipeline stall only in response to a determination that a speculative dependency exists.