Patents Examined by Scott Wilson
  • Patent number: 8207555
    Abstract: The present invention provides a light-emitting element having less increase in driving voltage with the accumulation of light-emission time, and provides a light-emitting element having less increase in resistance value with the increase in film thickness. A light-emitting element includes a first layer, a second layer and a third layer between a first electrode and a second electrode. The first layer is provided to be closer to the first electrode than the second layer, and the third layer is provided to be closer to the second electrode than the second layer. The first layer is a layer including an aromatic amine compound and a substance showing an electron accepting property to the aromatic amine compound. The second layer includes a substance of which an electron transporting property is stronger than a hole transporting property, and a substance showing an electron donating property to the aforementioned substance.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: June 26, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Kumaki, Satoshi Seo
  • Patent number: 8063437
    Abstract: A semiconductor device includes: a first semiconductor region formed on a substrate and having an upper surface and a side surface; a first impurity region of a first conductivity type formed in an upper portion of the first semiconductor region; a second impurity region of a first conductivity type formed in a side portion of the first semiconductor region; and a gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the first semiconductor region. A radius of curvature r? of an upper corner of a portion of the first semiconductor region located outside the gate insulating film is greater than a radius of curvature r of an upper corner of a portion of the first semiconductor region located under the gate insulating film and is less than or equal to 2r.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: November 22, 2011
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Keiichi Nakamoto, Hisataka Kanada, Bunji Mizuno
  • Patent number: 8017965
    Abstract: A semiconductor light emitting device is provided. The semiconductor light emitting device includes a first conductive semiconductor layer; an active layer on the first conductive semiconductor layer; a first quantum dot layer on the active layer; and a second conductive semiconductor layer on the first quantum dot layer.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: September 13, 2011
    Assignee: LG Innotek Co., Ltd.
    Inventor: Kyung Jun Kim
  • Patent number: 8017953
    Abstract: An LED chip is specified that comprises at least one current barrier. The current barrier is suitable for selectively preventing or reducing, by means of a reduced current density, the generation of radiation in a region laterally covered by the electrical connector body. The current spreading layer contains at least one TCO (Transparent Conductive Oxide). In a particularly preferred embodiment, at least one current barrier is contained which comprises material of the epitaxial semiconductor layer sequence, material of the current spreading layer and/or an interface between the semiconductor layer sequence and the current spreading layer. A method for producing an LED chip is also specified.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: September 13, 2011
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Berthold Hahn, Ralph Wirth, Tony Albrecht, Magnus Ahlstedt, Stefan Illek, Klaus Streubel
  • Patent number: 8008668
    Abstract: LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: August 30, 2011
    Inventor: Chien-Min Sung
  • Patent number: 8008771
    Abstract: A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: August 30, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pyoung-Wan Kim, Eun-Chul Ahn, Jong-Ho Lee, Teak-Hoon Lee, Chul-Yong Jang
  • Patent number: 7994521
    Abstract: Light-emitting devices, and related components, systems and methods are disclosed.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: August 9, 2011
    Assignee: Luminus Devices, Inc.
    Inventors: Alexei A. Erchak, Elefterios Lidorikis, Chiyan Luo
  • Patent number: 7994550
    Abstract: A semiconductor structure comprising: a substrate; a seed layer supported by the substrate; an elemental semiconductor layer disposed over a first portion of the seed layer; and a compound semiconductor layer disposed on a second portion of the seed layer. The first portion of the seed layer is electrically insulated from the second portion of the seed layer. A first semiconductor device is formed in the elemental semiconductor layer. A second semiconductor device is formed in the compound semiconductor layer. The second semiconductor device includes: a first electrode in contact with a first region of the compound semiconductor layer; a second electrode in contact with a second region of the compound semiconductor layer; and a third electrode. The third electrode controls carriers passing in a third region of the compound semiconductor layer disposed between the first region and the second region. A fourth electrode is in electrical contact with the second portion of the seed layer.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: August 9, 2011
    Assignee: Raytheon Company
    Inventors: Valery S. Kaper, John P. Bettencourt, Jeffrey R. LaRoche, Kamal Tabatabaie
  • Patent number: 7989816
    Abstract: A semiconductor device is, constituted by: a nitride group semiconductor functional layer which includes a first nitride group semiconductor region, a second nitride group semiconductor region provided on the first nitride group semiconductor region by a hetero junction, and a two-dimensional carrier gas channel near the hetero junction of the first nitride group semiconductor region; a first main electrode and a second main electrode connected to the two-dimensional carrier gas channel by ohmic contact; and a gate electrode disposed between the first main electrode and the second main electrode. The nitride group semiconductor region has different thicknesses between the second main electrode and the gate electrode, and between the first main electrode and the gate electrode.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: August 2, 2011
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Ken Sato
  • Patent number: 7985977
    Abstract: Briefly, in accordance with one or more embodiments, a dielectric platform is at least partially formed in a semiconductor substrate and extending at least partially below a surface of a semiconductor substrate. The dielectric platform may include structural pillars formed by backfilling a first plurality of cavities etched in the substrate, and a second plurality of cavities formed by etching away sacrificial pillars disposed between the structural pillars. The second plurality of cavities may be capped to hermetically seal the second plurality of cavities to impart the dielectric constant of the material contained therein, for example air, to the characteristic dielectric constant of the dielectric platform. Alternatively, the second plurality of cavities may be backfilled with a material having a lower dielectric constant than the substrate, for example silicon dioxide where the substrate comprises silicon.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: July 26, 2011
    Assignee: HVVi Semiconductors, Inc.
    Inventors: Bishnu Prasanna Gogoi, David William Wolfert, Jr.
  • Patent number: 7982247
    Abstract: A semiconductor device and method of making comprises providing an active device region and an isolation region, the isolation region forming a boundary with the active device region. A patterned gate material overlies the active device region between first and second portions of the boundary. The patterned gate material defines a channel within the active device region, the gate material having a gate length dimension perpendicular to a centerline along a principal dimension of the gate material which is larger proximate the first and second portions of the boundary than in-between the first and second portions of the boundary. The channel includes a first end proximate the first portion of the boundary and a second end proximate the second portion of the boundary, further being characterized by gate length dimension tapering on both ends of the channel.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: July 19, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Lionel J. Riviere-Cazaux
  • Patent number: 7982206
    Abstract: A light emitting device having high definition, a high aperture ratio, and high reliability is provided. The present invention achieves high definition and a high aperture ratio with a full color flat panel display using red, green, and blue color emission light by intentionally forming laminate portions, wherein portions of different organic compound layers of adjacent light emitting elements overlap with each other, without depending upon the method of forming the organic compound layers or the film formation precision.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: July 19, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Toru Takayama
  • Patent number: 7977705
    Abstract: In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: July 12, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bich-Yen Nguyen, Carlos Mazure
  • Patent number: 7973332
    Abstract: An LED lamp includes a board, a metal wiring provided on the board, an LED mounted on the metal wiring, and a metal heat dissipation film mainly made of a metal different from a metal for forming the metal wiring. The metal heat dissipation film partially overlaps the metal wiring. The metal heat dissipation film has an irregular surface. The metal heat dissipation film is mainly made of a metal that is softer than the metal wiring. The metal heat dissipation film intervenes between the board and the metal wiring, and part of the metal heat dissipation film that is in contact with the metal wiring has an irregular surface.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: July 5, 2011
    Assignee: Rohm Co., Ltd.
    Inventor: Hiroyuki Fukui
  • Patent number: 7973334
    Abstract: The present invention provides an ESD device to reduce the total triggering current without increasing the overshoot voltage. This is achieved by localizing the triggering current, such that the local current density remains high enough to trigger the ESD device. This localized triggering provides a fast and efficient triggering of the ESD device.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: July 5, 2011
    Assignee: Sofics BVBA
    Inventors: Stefaan Verleye, Geert Wybo, Benjamin Van Camp
  • Patent number: 7973374
    Abstract: Embodiments relate to a semiconductor device and a method for fabricating the same. According to embodiments, a semiconductor device may include a metal film spaced from a semiconductor substrate at a predetermined interval and in which a plurality of etching holes are formed. A bottom metal pattern disposed on and/or over a space between the semiconductor substrate and metal film and top metal pattern formed on and/or over the bottom metal pattern may be provided. A pillar may be formed on and/or over the semiconductor substrate and may support one side of a low surface of the bottom metal pattern. A pad may be formed on and/or over the semiconductor substrate, and an air layer corresponding to the bottom metal pattern may be inserted therein. According to embodiments, a pyro-electric switch transistor using a bi-metal with different coefficients of thermal expansion may be provided.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: July 5, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Eun-Soo Jeong
  • Patent number: 7968873
    Abstract: The present invention relates to an organic light emitting device and a manufacturing method thereof. The organic light emitting device according to an exemplary embodiment of the present invention includes a first thin film transistor disposed on a substrate, an organic layer disposed on the first thin film transistor, a pixel electrode disposed on the organic layer and connected to the first thin film transistor, a partition disposed on the pixel electrode and the organic layer, and an organic emission layer disposed on the pixel electrode and contacting the partition. The partition has an organic layer exposing hole that exposes a portion of the organic layer and an opening that exposes a portion of the pixel electrode.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: June 28, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Pil Lee, Chang-Woong Chu, Jin-Koo Chung, Chang-Mo Park
  • Patent number: 7956353
    Abstract: By introducing new concepts into a structure of a conventional organic semiconductor element and without using a conventional ultra thin film, an organic semiconductor element is provided which is more reliable and has higher yield. Further, efficiency is improved particularly in a photoelectronic device using an organic semiconductor. Between an anode and a cathode, there is provided an organic structure including alternately laminated organic thin film layer (functional organic thin film layer) realizing various functions by making an SCLC flow, and a conductive thin film layer (ohmic conductive thin film layer) imbued with a dark conductivity by doping it with an acceptor and a donor, or by the like method.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: June 7, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuo Tsutsui, Hiroko Yamazaki, Satoshi Seo
  • Patent number: 7956348
    Abstract: A quantum device comprises first conductive members and second conductive members confining carriers in the z direction and having two dimensional electron gas on the xy plane. Third conductive members generating an electric field having an effect on the first conductive members. An insulating member easily passing a tunnel current between the first conductive members and the second conductive members. Another insulating member hardly passing a tunnel current between the first conductive members and the third conductive members. An electric field generated by a potential applied to the third conductive members has an effect on the sub-band of the first conductive members.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: June 7, 2011
    Assignee: International Business Machines Corporation
    Inventor: Yasunao Katayama
  • Patent number: 7956390
    Abstract: A semiconductor device having a semiconductor substrate, a first impurity region including a first conductive impurity formed in the semiconductor substrate, a first transistor and a second transistor formed in the first impurity region, a first stress film and a second stress having a first stress over the first transistor a and the second transistor, and a third stress film having a second stress different from the first stress provided in the first impurity region between the first stress film and the second stress film.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: June 7, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Manabu Kojima