Abstract: A method of making an integrated circuit includes steps of etching an opening in an insulating mask to expose a first dummy contact on a backside of the integrated circuit, depositing a conductive material into the opening, the conductive material contacting a sidewall of the first dummy contact, and recessing the conductive material to expose an end of the first dummy contact. The method also includes steps of depositing an insulating material over the conductive material in the opening, removing the first dummy contact from the insulating mask to form a first contact opening, and forming a first conductive contact in the first contact opening, the first conductive contact being electrically connected to the conductive material.

Abstract: An additional set of interconnects is created in bulk material, allowing connections to active devices to be made from both above and below. The interconnects below the active devices can form a power distribution network, and the interconnects above the active devices can form a signaling network. Various accommodations can be made to suit different applications, such as encapsulating buried elements, using sacrificial material, and replacing the bulk material with a dielectric. Epitaxial material can be used throughout the formation process, allowing for the creation of a monolithic substrate.

Abstract: Source/drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source/drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source/drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source/drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source/drain feature where the silicide feature extends into the source/drain feature towards the substrate to a depth of the first channel layer.

Abstract: Provided is a semiconductor structure with shared gated devices. The semiconductor structure comprises a substrate and a bottom dielectric isolation (BDI) layer on top of the substrate. The structure further comprises a pFET region that includes a p-doped Source-Drain epitaxy material and a first nanowire matrix above the BDI layer. The structure further comprises an nFET region that includes a n-doped Source-Drain epitaxy material and a second nanowire matrix above the BDI layer. The structure further comprises a conductive gate material on top of a portion of the first nanowire matrix and the second nanowire matrix. The structure further comprises a vertical dielectric pillar separating the pFET region and the nFET region. The vertical dielectric pillar extends downward through the BDI layer into the substrate. The vertical dielectric pillar further extends upward through the conductive gate material to a dielectric located above the gate region.

Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor including: a plurality of source channels penetrating a source select line; a gate stack structure overlapping with the source select line; a connection pattern disposed between the source select line and the gate stack structure, the connection pattern being commonly connected to the plurality of source channels; and a plurality of vertical channels penetrating the gate stack structure, the plurality of vertical channels being commonly connected to the connection pattern.

Abstract: Embodiments of the application provide a display panel, a display screen and a display device. The display panel includes a backplane, a color filter layer, and a black matrix between the backplane and the color filter layer. The backplane includes a base substrate, the color filter layer includes a plurality of sub-pixel color filters, and the plurality of sub-pixel color filters are arranged along a plane of the color filter layer and spliced together to form the color filter layer.

Abstract: A crosstalk-suppressing image sensor includes a semiconductor substrate, an opaque layer, and a spectral filter. The semiconductor substrate includes a photodiode therein and is located beneath a light-exposure region of a back surface of the semiconductor substrate. The opaque layer is on the back surface, partially covers the light-exposure region, and has an opaque-layer thickness perpendicular to an image-plane direction parallel to the back surface. The spectral filter is adjacent to the opaque layer in the image-plane direction, and partially covers the light-exposure region.

Abstract: A method for transferring a useful layer from a donor substrate to a carrier substrate comprises: a) providing the donor substrate, the donor substrate including a buried weakened plane; b) providing the carrier substrate; c) joining the donor substrate to the carrier substrate to form a bonded structure; and d) annealing the bonded structure in order to increase the level of weakening of the buried weakened plane. A predetermined stress is applied to the buried weakened plane during the annealing for a period of time, the predetermined stress being selected so as to initiate the splitting wave once a given level of weakening has been reached. At the end of the period of time, the given level of weakening having been reached, the predetermined stress causes initiation and self-sustained propagation of the splitting wave along the buried weakened plane, resulting in the useful layer being transferred to the carrier substrate.

Abstract: A semiconductor device includes a substrate having a first region, a second region, and a third region with gate electrodes spaced apart from each other in the first region and the second region. The semiconductor device also includes interlayer insulating layers alternately stacked with the gate electrodes, channel structures passing through the gate electrodes in the first region, first dummy structures passing through the gate electrodes in the second region, the first dummy structures disposed adjacent to the first region, second dummy structures passing through the gate electrodes in the second region, the second dummy structures disposed adjacent to the third region, and having different shapes from the first dummy structures, and support structures passing through the gate electrodes in the third region. A size of each of the second dummy structures is larger than a size of each of the support structures.

Abstract: A display apparatus includes a substrate including a display area and a peripheral area outside the display area, a thin film transistor arranged on the substrate corresponding to the display area and including a semiconductor layer and a gate electrode, a pad electrode arranged on the substrate corresponding to the peripheral area and including a material the same as that of the semiconductor layer, and a first insulating layer arranged on the thin film transistor and the pad electrode and including an opening that partially exposes the pad electrode. Accordingly, failure to perform a normal operation by a pixel circuit and a light-emitting element may be prevented.

Abstract: A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, the electrodes including pad portions on the connection region, respectively, and the pad portions of the electrodes being stacked in a staircase structure, first vertical structures penetrating the electrode structure on the cell array region, and second vertical structures penetrating the electrode structure on the connection region, each of the second vertical structures including first parts spaced apart from each other in a first direction, and at least one second part connecting the first parts to each other, the at least one second part penetrating sidewalls of the pad portions, respectively.

Abstract: A method includes forming a 2-D material semiconductor layer over a substrate; forming source/drain electrodes covering opposite sides of the 2-D material semiconductor layer, while leaving a portion of the 2-D material semiconductor layer exposed by the source/drain electrodes; forming a first gate dielectric layer over the portion of the 2-D material semiconductor layer by using a physical deposition process; forming a second gate dielectric layer over the first gate dielectric layer by using a chemical deposition process, in which a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer; and forming a gate electrode over the second gate dielectric layer.

Abstract: A display substrate having a plurality of subpixels is provided. A respective one of the plurality of subpixels includes a light emitting element; a first thin film transistor configured to driving light emission of the light emitting element; and a light emitting brightness value detector. The light emitting brightness value detector includes a second thin film transistor; and a photosensor electrically connected to the second thin film transistor and configured to detect a light emitting brightness value. The display substrate further includes a silicon organic glass layer on a side of at least one of the first thin film transistor or the second thin film transistor away from a base substrate; and the photosensor is on a side of the silicon organic glass layer away from the base substrate.

Abstract: In an embodiment, the semiconductor device is surface mountable and comprises a light emitting semiconductor chip which comprises electrical contact pads. An opaque base body laterally surrounds the semiconductor chip. An electrical fanning layer contains electrical conductor tracks. Electrical connection pads are used for external electrical contacting of the semiconductor device. The contact pads and the connection pads are located on different sides of the fanning layer. The contact pads are electrically connected to the associated connection pads by means of the fanning layer. The connection pads are expanded relative to the contact pads.

Abstract: An image sensor comprises a first photodiode region and circuitry. The first photodiode region is disposed within a semiconductor substrate proximate to a first side of the semiconductor substrate to form a first pixel. The first photodiode region includes a first segment coupled to a second segment. The circuitry includes at least a first electrode associated with a first transistor. The first electrode is disposed, at least in part, between the first segment and the second segment of the first photodiode region such that the circuity is at least partially surrounded by the first photodiode region when viewed from the first side of the semiconductor substrate.

Abstract: Integrated circuit structures having linerless self-forming barriers, and methods of fabricating integrated circuit structures having linerless self-forming barriers, are described. In an example, an integrated circuit structure includes a dielectric material above a substrate. An interconnect structure is in a trench in the dielectric material. The interconnect structure includes a conductive fill material and a two-dimensional (2D) crystalline liner. The 2D crystalline liner is in direct contact with the dielectric material and with the conductive fill material. The 2D crystalline liner includes a same metal species as the conductive fill material.

Abstract: A method for manufacturing a three-dimensional memory device comprises: forming a first pre-stack by alternately stacking a plurality of first interlayer dielectric layers and a plurality of first sacrificial layers in a vertical direction; forming, in the first pre-stack, a first staircase part; forming a plurality of first vertical vias, which pass through the first staircase part, and a plurality of second vertical vias that pass through a first coupling part of the first pre-stack; forming a second pre-stack by alternately stacking a plurality of second interlayer dielectric layers and a plurality of second sacrificial layers on the first pre-stack; forming, in the second pre-stack, a second staircase part; forming a plurality of third vertical vias and a plurality of fourth vertical vias; and replacing the first and second sacrificial layers with an electrode material.

Abstract: A vertical memory device includes a gate electrode structure formed on a substrate including a cell array region and a pad region, a channel, contact plugs, and support structures. The gate electrode structure includes gate electrodes extending in a second direction and stacked in a staircase shape in a first direction on the pad region. The channel extends through the gate electrode structure on the cell array region. The contact plugs contact corresponding ones of steps, respectively, of the gate electrode structure. The support structures extend through the corresponding ones of the steps, respectively, and extend in the first direction on the pad region. The support structure includes a filling pattern and an etch stop pattern covering a sidewall and a bottom surface thereof. An upper surface of each of the support structures is higher than that of the channel.

Abstract: Provided is a display device which comprises a substrate, a plurality of pixels disposed on the substrate, a first initialization voltage line disposed on the substrate along a first direction, and a second initialization voltage line disposed on a different layer from the first initialization voltage line, wherein the second initialization voltage line may include a horizontal portion disposed along the first direction and a vertical portion disposed along a second direction crossing the first direction, and the vertical portion may be disposed between a plurality of pixels adjacent to each other in the first direction.