Patents Examined by Sean Fletcher
  • Patent number: 7164148
    Abstract: A CAN package light emitting device comprises a semiconductor laser 1 bonded on a sub mount 6 and a CAN package 2 for housing the semiconductor laser 1 bonded on the sub mount 6. The CAN package 2 comprises a fixing structure 3 for fixing the semiconductor laser at a predetermined position, and a cap 4 covering the semiconductor laser 1 fixed to the fixing structure 3. Vapor pressure of Si organic compound gas in the CAN package 2 is limited to or below 5.4×102 N/m2 to prevent any deposit as thick as inviting characteristics deterioration from being formed on the light emitting portion of the semiconductor laser 1 within the guaranteed time of its proper operation.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: January 16, 2007
    Assignee: Sony Corporation
    Inventors: Hiroshi Yoshida, Tadashi Taniguchi, Takashi Mizuno
  • Patent number: 7126207
    Abstract: In one embodiment, a capacitor comprises a substrate defining a first electrical terminal; a catalyst layer disposed on the substrate; a plurality of carbon nanotubes disposed on the catalyst layer; a dielectric layer disposed over the plurality of carbon nanotubes; and a conductive layer disposed on the dielectric layer and defining a second electrical terminal.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: October 24, 2006
    Assignee: Intel Corporation
    Inventors: Larry E. Mosley, Quat T. Vu, Yuegang Zhang
  • Patent number: 7126177
    Abstract: Disclosed are a semiconductor memory device, a semiconductor device, and a method for production thereof. The semiconductor memory device and semiconductor device do not need for a distance for alignment of lithography to make the contact hole with lithography to form the gate electrode. Hence the resulting devices have a reduced area for the cell array. The semiconductor memory device is composed of a substrate having trenches formed side by side, a plate electrode which is formed to a prescribed depth from the surface of the inner wall of the trench, a capacitor insulating film which covers the surface of the inner wall of the trench, a memory node electrode MN which fills the trench, with the capacitor insulating film interposed between them, and a memory node contact plug which is buried in a contact hole which is so made as to reach the memory node electrode from the surface of the semiconductor layer.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: October 24, 2006
    Assignee: Sony Corporation
    Inventors: Yuzo Fukuzaki, Hiroshi Takahashi
  • Patent number: 7105850
    Abstract: Disclosed is a GaN LED structure with a p-type contacting layer using Al—Mg-codoped In1?yGayN grown at low temperature, and having low resistivity. The LED structure comprises, from the bottom to top, a substrate, a buffer layer, an n-type GaN layer, an active layer, a p-type shielding layer, and a p-type contacting layer. In this invention, Mg and Al are used to co-dope the In1?yGayN to grow a low resistive p-type contacting layer at low temperature. Because of the Al—Mg-codoped, the light absorption problem of the p-type In1?yGayN layer is improved. The product, not only has the advantage of convenience of the p-type contacting layer for being manufactured at low temperature, but also shows good electrical characteristics and lowers the operating voltage of the entire element so that the energy consumption during operation is reduced and the yield rate is increased.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: September 12, 2006
    Assignee: Formosa Epitaxy Incorporation
    Inventors: Liang-Wen Wu, Ru-Chin Tu, Cheng-Tsang Yu, Tzu-Chi Wen, Fen-Ren Chien
  • Patent number: 7045871
    Abstract: Since a ZnTe-base compound semiconductor crystal was designed so as to have, on a ZnTe-base compound semiconductor layer, an n-type contact layer which includes a superlattice layer having n-type CdSe and n-type ZnTe grown with each other or a ZnCdSeTe-graded layer, it was made possible to raise carrier concentration of the n-type contact layer, and to control the conductivity type in a relatively easy manner. Moreover, formation of a CdSe/ZnTe superlattice layer or a ZnCdSeTe-graded layer between the contact layer and an electrode can prevent electric resistance from being increased due to difference in the energy gaps. Since CdSe and ZnTe, composing the CdSe/ZnTe superlattice or ZnCdSeTe composition-graded layer, have relatively close lattice constants, formation thereof is less likely to adversely affect the crystallinity of the semiconductor crystal, which is advantageous in obtaining the semiconductor crystal with an excellent quality.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: May 16, 2006
    Assignees: Nikko Materials Co., Ltd.
    Inventors: Katsumi Kishino, Ichiro Nomura, Song-Bek Che, Kenji Sato