Abstract: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.

Abstract: A storage interfacing method and apparatus for a mobile terminal are disclosed. The storage interfacing method utilizes a plurality of storage devices. The method includes identifying the storage devices, detecting an occurrence of an access request event to one of the identified storage devices, determining whether the access-requested storage device is an access-selected storage device, and performing, if the access-requested storage device is an access-selected storage device, a data transfer operation associated with the access request event on the access-selected storage device without access initialization and access-selection. The apparatus includes a first storage device supporting a MultiMediaCard (MMC) interface, a second storage device compatible with the MMC interface, and a control unit for controlling the first and second storage devices, according to the MMC interface, through control and data buses shared by the first and second storage devices.

Abstract: Methods, apparatus, and products are disclosed for optimizing execution of Input/Output (‘I/O’) requests for a disk drive in a computing system that include: receiving I/O requests specifying disk blocks of the disk drive for access, each disk block specified by a disk drive head, a cylinder, and a sector of the disk drive; determining I/O sub-requests from the I/O requests, each I/O sub-request specifying a set of adjacent disk blocks along the same cylinder; determining execution sequences for performing the I/O sub-requests; calculating, for each execution sequence, a total estimated execution time for performing the I/O sub-requests according to that execution sequence; selecting one of the execution sequences for performing the I/O sub-requests in dependence upon the total estimated execution times for the execution sequences; and instructing a disk drive controller to perform the I/O requests by performing the I/O sub-requests according to the selected execution sequence.

Abstract: Software assists a processor subsystem in making cache replacement decisions by providing an intermediary with information regarding how instructions and/or data of a working set are expected to be used and accessed by the software. The intermediary uses this information along with its knowledge of system requirements, policy and the cache configuration to determine cache usage and management hints for the working sets. The cache usage and management hints are passed by the intermediary to the processor subsystem.

Abstract: A semiconductor memory (2) comprises a controller (21) and a memory array (22). The memory array (22) is controlled for each of block areas (221, 221 . . . ). The information processing apparatus (1) can not generate a data erase command for each block area (221). A data erase command (30) for a specified block area “G” is encoded and stored in a block area “A”. When a request for data erasing is issued, a CPU (11) of the information processing apparatus (1) reads an erase command (30) out from the semiconductor memory (2) and outputs the erase command (30) to the controller (21). The controller (21) decodes the erase command (30) and performs a data erasing process for the block area “G”.

Abstract: An improved reader-writer locking for synchronizing access to shared data. When writing the shared data, a writer flag is set and a lock is acquired on the shared data. The shared data may be accessed following the expiration of a grace period and a determination that there are no data readers accessing the shared data. When reading the shared data, the writer flag is tested that indicates whether a data writer is attempting to access the shared data. If the writer flag is not set, the shared data is accessed using a relatively fast read mechanism. If the writer flag is set, the shared data is accessed using a relatively slow read mechanism.

Abstract: An apparatus for processing information, includes a memory storing a plurality of content items different in type and metadata containing time information of the content items, a cache processor for fetching from the memory the content item and the metadata of the content item to be displayed on a display and storing the fetched content item and the metadata thereof on a cache memory, a display controller for displaying on the display the metadata of the content items from the cache memory arranged in accordance with the time information and a selection operator selecting metadata corresponding to a content item desired to be processed, out of the metadata displayed, and a content processor for fetching from the cache memory a content item corresponding to the metadata selected by the selection operator by referencing the cache memory in response to the selected metadata, and for performing a process responsive to the fetched content item.

Abstract: A storage resource including one or more first storage devices; a first logical volume formed according to storage space of the storage resource; a member for accommodating a removable second storage device selected by a user; and a backup unit, the backup unit executing a backup of data stored in the first logical volume to a second logical volume formed according to storage space of the removable second storage device mounted in the member and paired with the first logical volume; and storing, in said storage resource, of backup generation information elements pertaining to what generation of the backup the current backup of the first logical volume is.

Abstract: A processor cache is indexed by a group of distinct page colors. The use of this cache by different working sets is controlled using page coloring. Translations of virtual addresses of the instructions and/or data of a working set are constrained to physical addresses the page colors of which are in a subgroup of the group of distinct page colors.

Abstract: Determining and applying a cache replacement policy for a computer application running in a computer processing system is accomplished by receiving a processor core data request, adding bits on each cache line of a plurality of cache lines to identify a core ID of an at least one processor core that provides each cache line in a shared cache, allocating a tag table for each processor core, where the tag table keeps track of an index of processor core miss rates, and setting a threshold to define a level of cache usefulness, depending on whether or not the index of processor core miss rates exceeds the threshold. Checking the threshold and when the threshold is not exceeded, then a shared cache standard policy for cache replacement is applied. When the threshold is exceeded, then the cache line from the processor core running the application is evicted from the shared cache.

Abstract: Systems and/or methods that facilitate reading data from a memory component associated with a network are presented. A pre-fetch generation component generates a pre-fetch request based in part on a received read command. To facilitate a reduction in latency associated with transmitting the read command via an interconnect network component to which the memory component is connected, the pre-fetch request is transmitted directly to the memory component bypassing a portion of the interconnect network component. The memory component specified in the pre-fetch request receives the pre-fetch request and reads the data stored therein, and can store the read data in a buffer and/or transmit the read data to the requester via the interconnect network component, even though the read command has not yet reached the memory component. The read data is verified by comparison with the read command at a convergence point.

Abstract: A flash memory system includes flash memory organized into a plurality of blocks of pages for storage of information, a page including data and spare, the blocks being identifiable, within the flash memory, by a physical address. The system further has a flash controller for communicating with a host and the flash memory and includes volatile memory for storing a source-shadow table of logical addresses identifying blocks addressable by the physical addresses. The source-shadow table has an address mapping table and a property value table. The property value table is used to store property values, each of which is associated with a block of a predetermined group of blocks and is indicative of the number of times a block has been written since the last erase operation performed thereon.

Abstract: A processor prevents writeback race condition errors by maintaining responsibility for data until the writeback request is confirmed by an intervention message from a cache coherency manager. If a request for the same data arrives before the intervention message, the processor core unit provides the requested data and cancels the pending writeback request. The cache coherency data associated with cache lines indicates whether a request for data has been received prior to the intervention message associated with the writeback request. The cache coherency data of a cache line has a value of “modified” when the writeback request is initiated. When the intervention message associated with the writeback request is received, the cache lines's cache coherency data is examined. A change in the cache coherency data from the value of “modified” indicates that the request for data has been received prior to the intervention and the writeback request should be cancelled.

Abstract: Livelocks are prevented in multiple core processors by canceling data access requests upon determining that they conflict with other data access requests. A requesting processor core sends a data access request potentially causing livelock to a cache coherency manager. A cache coherency manager receives data access requests from multiple processor. The cache coherency manager sends intervention messages to all of the processor cores in response to all data access requests that may cause livelock. Upon receiving an intervention message from the cache coherency manager, the processor core determines if the intervention message corresponds with any of its own pending data access requests. If the intervention message is associated with a data access request conflicting with one of its own pending data access requests, the processor core responds to the invention message by directing the cache coherency manager to cancel its own conflicting pending data access request.

Abstract: The invention discloses a memory control system and a method to read data from memory. The memory control system comprises a microprocessor, a serial storage device, a first buffer, a second buffer, a memory control unit, and a multiplexer. The memory control system and the method to read data from memory according to the invention utilize the characteristics that the microprocessor reads data from continuous addresses of a serial memory during most of the time. By reading in advance and temporarily storing the data that the microprocessor requests to read, increasing the reading memory speed can be achieved.

Abstract: A processor cache is indexed by a group of distinct page colors. The use of this cache by different working sets is controlled using page coloring. Translations of virtual addresses of the instructions and/or data of a working set are constrained to physical addresses the page colors of which are in a subgroup of the group of distinct page colors.

Abstract: Livelocks are prevented in multiple core processors by verifying that a data access request is still valid before sending messages to processor cores that may cause other data access requests to fail. A cache coherency manager receives data access requests from multiple processor cores. Upon receiving a data access request that may cause a livelock, the cache coherency manager first sends an intervention message back to the requesting processor core to confirm that this data access request will succeed. If the requesting processor core determines that the data access request is still valid, it directs the cache coherency manager to proceed with the data access request. The cache coherency manager may then send intervention messages to other processor cores to complete the data access request. If the requesting processor core determines that the data access request is invalid, it directs the cache coherency manager to abandon the data access request.

Abstract: An apparatus for processing information, includes a memory storing a plurality of content items different in type and metadata containing time information of the content items, a cache processor for fetching from the memory the content item and the metadata of the content item to be displayed on a display and storing the fetched content item and the metadata thereof on a cache memory, a display controller for displaying on the display the metadata of the content items from the cache memory arranged in accordance with the time information and a selection operator selecting metadata corresponding to a content item desired to be processed, out of the metadata displayed, and a content processor for fetching from the cache memory a content item corresponding to the metadata selected by the selection operator by referencing the cache memory in response to the selected metadata, and for performing a process responsive to the fetched content item.