Abstract: A GOA circuit, a display panel and a display device are provided. The GOA circuit includes a plurality of GOA units connected in series. The GOA unit includes a forward scan control module, a node signal control module, an output control module, a regulating module, a first pull-down module, a second pull-down module, a third pull-down module, a fourth pull-down module, and a switch module. The display device according to an embodiment only needs two clock signals for the GOA driving circuit to scan each row of gates. Furthermore, it could enormously reduce the width of GOA and realize the narrow side frame design.
Abstract: A voltage stabilization circuit includes a first sub-circuit. The first sub-circuit includes a first voltage stabilizing element; a first switching element; and a second switching element. For the first voltage stabilizing element, the first terminal is electrically connected to a first node, and the second terminal is grounded. For the first switching element, the first terminal is electrically connected to the first node, and the second terminal is electrically connected to a voltage stabilizing target. For the second switching element, the first terminal is electrically connected to the control terminal of the first switching element, and the control terminal is electrically connected to the first node. When the first voltage stabilizing element is in a first operating state, the second switching element is turned on, and the first switching element is turned off.
Abstract: A shift register includes an output sub-circuit, a cascade sub-circuit and at least one additional output sub-circuit. The output sub-circuit is configured to transmit a first clock signal received at the first clock signal terminal to the output signal terminal under control of a potential at the pull-up node, so as to scan a gate line coupled to the output signal terminal. The cascade sub-circuit is configured to transmit a second clock signal received at the second clock signal terminal to the cascade node under the control of the potential at the pull-up node. Each additional output sub-circuit is configured to transmit a clock signal received at a corresponding clock signal terminal to a corresponding additional output signal terminal under control of a potential at the cascade node, so as to scan a gate line coupled to the corresponding additional output signal terminal.
Abstract: A printed wiring line formed on a substrate connects two different points on the substrate which are connectable by another printed wiring line with a shape of a straight-line segment and has a shape corresponding to at least one of: 1) a shape with no linear part parallel to the straight-line segment; 2) a shape with line segments connected in series, each line segment having a shape with no linear part parallel to the straight-line segment; 3) a shape having a part parallel to the straight-line segment and a part not parallel to the straight-line segment, length of the part parallel to the straight-line segment being not more than length of the straight-line segment; and 4) a shape in which line segments are connected in series, each line segment having a shape having a part parallel to the straight-line segment and a part not parallel to the straight-line segment.
Type:
Grant
Filed:
July 17, 2020
Date of Patent:
April 19, 2022
Assignee:
JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
Abstract: A shift register includes a first transistor, a second transistor, a pull-up node and a switch sub-circuit. A control electrode of the first transistor is connected to a signal input terminal, a first electrode of the first transistor is connected to a first voltage terminal, and a second electrode of the first transistor is connected to a first control node. A control electrode of the second transistor is connected to a reset signal terminal, a first electrode of the second transistor is connected to a second voltage terminal, and a second electrode of the second transistor is connected to the first control node. The switching sub-circuit is connected to the first control node and the pull-up node, and is configured to control a line between the first control node and the pull-up node to be closed and opened.
Abstract: Disclosed is an output buffer circuit for a display driving apparatus, which generates an output voltage by using a bias current controlled by digital-to-analog conversion for interpolation data, the output buffer circuit including a decoder configured to output control data obtained by decoding interpolation data, and an output circuit configured to output an output voltage by using a bias current having the amount of current controlled by digital-to-analog conversion for the control data.
Type:
Grant
Filed:
July 6, 2021
Date of Patent:
April 19, 2022
Assignee:
Silicon Works Co., Ltd
Inventors:
Young Bok Kim, Taiming Piao, Young Tae Kim, Young Ho Shin
Abstract: A circuit device configured to drive an electro-optical panel including a demultiplexer provided between a first to n-th data lines, n being an integer of three or greater, and a data signal supply line, includes a data line driving circuit configured to output a data signal to the data signal supply line, and a processing circuit configured to set a selection order, by the demultiplexer, of the first to n-th data lines. When an i-th data line, i being an integer of 1 to n, is selected j-th, j being an integer of 1 to n, in the first selection order, the processing circuit sets a second selection order using random number information so as to prohibit the i-th data line from being selected j-th in the second selection order.
Abstract: The disclosure provides a timing control method and a timing control circuit for a display panel, a driving device, and a display device. The method includes: in respective display periods, supplying a data enable signal to a source driving circuit. The source driving circuit supplies a data signal to a plurality of sub-display regions under the control of the data enable signal. The data enable signal is switched between an active level and an inactive level, and the active levels of the data enable signal are in one-to-one correspondence with the plurality of sub-display regions of the display panel. The farther one of the plurality of sub-display regions from the source driving circuit, the longer time period, at an active level, of the data enable signal for controlling the source driving circuit to provide the data signal to at least one row of pixels in the sub-display region is.
Abstract: An HMD includes an image display section configured to display an image to be visually recognizable through an outside scene. The HMD includes a position detecting section configured to recognize an input and a control section configured to cause the image display section to display information and change the display in the image display section according to the input recognized by the position detecting section.
Type:
Grant
Filed:
June 24, 2021
Date of Patent:
April 12, 2022
Assignee:
SEIKO EPSON CORPORATION
Inventors:
Kazuo Nishizawa, Masahide Takano, Teruhito Kojima
Abstract: This application discloses a display panel and a display apparatus. The display panel includes a first signal line and a second signal line; an overlapping region is formed at an intersection of the second signal line and the first signal line; and the first signal line includes at least two sub-connection lines and the connection line crosses the overlapping region.
Abstract: The present disclosure provides a driving method, a driving circuit, and a display device. The driving method includes steps of receiving a data signal of a first standard, generating a first data frame, and driving a display panel at a refresh frequency of the first data frame and receiving the data signal of the second standard, calculating and generating at least one transition frame according to the data signal of the first standard and the data signal of the second standard, and driving the display panel at a refresh frequency corresponding to the at least one transition frame. A refresh frequency of the at least one transition frame is between a refresh frequency of the first data frame and a refresh frequency of the second data frame.
Abstract: The present application discloses a shift-register circuit used as a shift-register unit of current stage including a control sub-circuit coupled to a shift-register unit of previous stage and configured to recharge a pull-up node of the shift-register unit of previous stage during a touch-control operation performed after a gate line scanning of previous stage ends and before the gate line scanning of current stage starts. The control sub-circuit is further configured to compensate an internal voltage of the shift-register unit of previous stage before the touch-control operation ends so that the shift-register unit of previous stage is triggered to perform the gate line scanning of previous stage followed by the shift-register unit of current stage to perform the gate line scanning of current stage.
Abstract: A shift register and a driving method thereof, a gate driving circuit and a display apparatus are disclosed. The shift register includes an input circuit, a pull-up node charging circuit and an output circuit. The pull-up node charging circuit is connected with a first voltage terminal, a second voltage terminal, the input circuit and a pull-up node, and is configured to charge the pull-up node and maintain a level of the pull-up node under control of the first input signal.
Abstract: A display device includes a display panel including a plurality of data lines, and a plurality of pixels coupled to the plurality of data lines, a data driver including a plurality of channels providing data voltages to the plurality of pixels through the plurality of data lines, and a controller configured to control the data driver. The plurality of channels is grouped into first through N-th channel groups, where N is an integer greater than 1. The first through N-th channel groups sequentially initiate first dummy data voltage output operations in a first order from the first channel group to the N-th channel group in a first blank period before an active period, and sequentially finish second dummy data voltage output operations in a second order from the N-th channel group to the first channel group in a second blank period after the active period.
Type:
Grant
Filed:
June 22, 2021
Date of Patent:
March 29, 2022
Inventors:
Taegon Im, Gwangsoo Ahn, Jong Jae Lee, Byungkil Jeon
Abstract: An electronic circuit, adapted to drive a display panel comprising touch sensors, is provided. The electronic circuit can include a display driving circuit, a timing circuit and a touch scan circuit. The display driving circuit drives a touch display panel. The timing circuit receives a flag signal from a processing circuit and generates a scan start signal according to the flag signal. The touch scan circuit generates a plurality of touch scan signals according to the scan start signal and a touch column synchronization signal. The touch scan circuit determines a start time of a touch frame period according to a pulse of the scan start signal. The scan start signal can be asynchronous or delayed with respect to a touch frame synchronization signal generated by the display driving circuit.
Type:
Grant
Filed:
August 17, 2020
Date of Patent:
March 29, 2022
Assignee:
Novatek Microelectronics Corp.
Inventors:
Chung-Cher Lin, Yun-Hsiang Yeh, Ta-Keng Weng, Yi-Min Li
Abstract: A touch substrate, a method of driving the same, and a touch display device are provided, and the touch substrate includes: a plurality of emitting electrode patterns arranged along a first direction, wherein the emitting electrode patterns includes an emitting electrode sub-pattern or a plurality of electrically connected emitting electrode sub-patterns; a plurality of first receiving electrode patterns arranged along a Y-direction, wherein the first receiving electrode patterns includes a plurality of electrically connected first receiving electrode sub-patterns; a plurality of second receiving electrode patterns arranged along an X-direction and insulated from the first receiving electrode pattern, and the second receiving electrode pattern includes a plurality of second receiving electrode sub-patterns electrically connected in sequence; the first direction intersecting both the X-direction and the Y-direction.
Abstract: A display device includes a backlight module, and the backlight module includes a light-guiding plate, a light-emitting assembly, and an adhesive member. The light-emitting assembly is disposed correspondingly to the light-guiding plate, and includes a substrate and a plurality of light-emitting elements. The substrate includes a component arrangement region and a planar region in a top view, and includes a base material layer, a filled layer and a protection layer in a sectional view. A thickness of the protection layer is greater than 0 ?m and less than 30 ?m. The light-emitting elements are located on the component arrangement region. The adhesive member connects the light-guiding plate and the planar region of the substrate. An assembling method of the display device is also provided. This disclosure can improve the non-uniform brightness issue (hotspots) or enhance the optical performance.
Abstract: This application provides a capacitance detection circuit, which is configured to detect a capacitance between a sensing electrode in a screen and a first driving electrode to which a driving signal is input. The capacitance detection circuit includes: an amplification circuit, connected to the sensing electrode and configured to convert a capacitance signal between the sensing electrode and the first driving electrode into a voltage signal; a cancellation circuit, connected to the amplification circuit and configured to output a cancellation signal to the amplification circuit, where the cancellation signal is used to cancel a noise signal from the screen included in the voltage signal; and a control circuit, connected to a second driving electrode, in the screen, to which no driving signal is input, and configured to generate a control signal, where the control signal is configured to control the cancellation circuit to generate the cancellation signal.
Abstract: A test apparatus includes: a compensation coefficient calculator configured to calculate a main compensation coefficient for a main gradation and a sub compensation coefficient for a sub gradation based on a detected image signal; a primary predictor configured to determine a representative value of each of a plurality of blocks of a display panel based on the detected image signal, and output a prediction compensation coefficient for the sub gradation based on the main compensation coefficient and the representative value corresponding to each of the plurality of blocks; a secondary predictor configured to determine a flag based on the sub compensation coefficient and the prediction compensation coefficient; and a controller configured to output the main compensation coefficient, the representative value, and the flag stored in a memory as compensation data.
Type:
Grant
Filed:
May 10, 2021
Date of Patent:
March 8, 2022
Inventors:
Hyunseuk Yoo, Ji-Eun Park, Hye-Sang Park, Seokha Hong
Abstract: Apparatuses, systems, and methods for interacting with media items in a virtual reality environment are provided. An apparatus is provided that includes processing circuitry configured to control a display of a virtual reality interface to render representations of media items in the virtual reality environment. The processing circuitry is further configured to control the display to render metadata links between a metadata attribute and the representations of the media items, detect, from a haptic interface, a haptic gesture to bundle and pull the metadata links into a foreground, and control the display to render representations of the media items having the metadata attribute in the foreground for selection.