Abstract: A semiconductor chip having improved heat dissipation capability. The back surface of a semiconductor chip is provided with microscopic channels defined by fins in intimate contact with the chip. A cover is affixed to the fins to enclose the channels for the laminar flow of coolant fluid. The chip can be mounted in a recessed portion of a dual in-line package (DIP) with conductive tubes integral with the package providing the flow of coolant. Advantageously, the tubes can function as power busses to the integrated circuit.

Abstract: One surface of a substrate of an LED module for a flat panel display has 8.times.8 element areas divided into a matrix form. Row electrodes extend on element areas arranged along the row direction, and column electrodes insulated from the row electrodes extend on element areas arranged in the column direction. At least one LED pellet is disposed for each element area and is connected to the row and column electrode associated with this area. A connecting pad is disposed as spaced apart from the four pellets in a unit area defined as a region consisting of four element areas. This connecting pad is connected to one of the row and column electrodes in the four element areas and is also connected through the substrate to a connecting pin arranged on the other surface of the substrate of the LED module.

Abstract: Aluminum electrically conducting patterns for integrated circuits are achieved with narrow lines and unexpectedly-high electromigration characteristics by making the crystal grains of the pattern into a chain-shaped structure with {111} orientation. A process for achieving the structure is also described.

Abstract: A cover with an electrically insulated current lead-through for closing cup-shaped compartments of electrical components includes a lead-through element in the form of a lead-through disc having a lead-through post extending therefrom, a permeation-proof and electrical insulating material disposed over one side of the lead-through disc, and a cover plate disposed over the electrical insulating material such that the latter is sandwiched between the cover plate and the lead-through disc. The cover plate and insulation material have openings through which the lead-through post extends, the insulating material having an outer edge portion extending along the outer edge and partially onto the opposite side of the lead-through disc, the cover plate, the electrical insulating material and the lead-through element being mechanically secured together.

Abstract: A glass-moulded type semiconductor device comprising semiconductor arrangement composed of at least one semiconductor pellet having at least one P-N junction, edges of which are exposed to peripheral surfaces of the semiconductor pellet, a pair of electrodes secured to opposite ends of the semiconductor arrangement through a brazing material, a first mould glass layer secured to the entire circumferential surface of the semiconductor arrangement and extending to the surfaces of the electrodes for passivating the P-N junction of the semiconductor arrangement, and a second mould glass in the form of at least one layer secured to the surface of said first mould glass layer.

Abstract: A cooling means for a semiconductor device comprises a heat radiating plate made of aluminum or aluminum alloy, having a fitting part for a semiconductor device; an alloy layer formed only at said fitting part of the heat radiating plate to allow easy soldering and a solder layer for bonding said semiconductor device to said alloy layer.

Abstract: A chip carrier having a plurality of leads thereon for external interconnection with preferably only one of the leads utilized to provide a source of power to the chip and preferably a single lead utilized as a ground connection. The power and ground leads are connected in a bus structure around the chip at the center of the chip carrier with the chip being secured to the chip carrier with the bus structure over a thermal pad formed within the bus structure. A decoupling capacitor is located in close proximity to the chip on the substrate to assure low reaction due to switching.

Abstract: Connection to a tantalum capacitor electrode (17) is effected using a conductive paint layer (15), incorporating pure silver and pure copper particles, which minimizes silver leeching by a tin-containing solder alloy (18) by which the lead wire (17) is connected to the conductive paint layer (15), and thus minimizes power factor degradation.

Abstract: A solid state electric double layer capacitor comprisinga polarization electrode,a non-polarization electrode, anda solid electrolyte disposed at least between the polarization electrode and the non-polarization electrode,the polarization electrode being a mixture of carbon and the solid electrolyte, mixed with each other in a predetermined ratio,the non-polarization electrode being another mixture of the solid electrolyte and a composition containing Cu and a substance selected from a group consisting of Cu.sub.2 S and TiS.sub.2, andthe solid electrolyte having a chemical composition of K.sub.x Rb.sub.1-x Cu.sub.4 I.sub.y Cl.sub.5-y (0.1.ltoreq.x .ltoreq.0.25, 1.25.ltoreq.y.ltoreq.1.67).

Abstract: A trim structure having a nominal resistance value can be adjusted to have a higher or lower value by a combination of fuse blowing and zener zapping. In the preferred embodiment a pair of integrated circuit pads are employed in a trim structure along with a pair of back-to-back zener diodes, a fuse link, and four resistors. In its initial state, with both diodes and the fuse link intact, a particular or nominal resistance value is available. Blowing the fuse link alone produces a second or highest resistance value. Shorting, or zapping, one zener diode produces a third higher than nominal but lower than highest resistance value. Shorting, or zapping, the other zener diode produces a fourth, lower than nominal, resistance value. Shorting, or zapping, both zener diodes produces a fifth lowest resistance value. Thus, five different resistance values are available using only two integrated circuit pads. If desired, the five resistance steps can be made linear by properly selecting the resistor values.

Abstract: A package and system for elimination or reduction to a minimum of reflection of the signal when transmitting from a substrate into an integrated circuit package at very high speed. This is accomplished by providing a conductor grid at a proper distance from a conductor plane to act as a reference ground plane. The grid is designed so that the difference of coefficient of expansion of the ceramic insulator and the metal conductors, which results in the deformation of the plane substrate surface due to "bimetallic" effects, is essentially cancelled due to the symmetrical construction with about the same amount of the same metal placed on both sides of the ceramic substrate. In this way, forces provided due to the thermal mismatch are mutually cancelled.

Abstract: A chip carrier having a plurality of leads thereon for external interconnection with preferably only one of the leads utilized to provide a source of power to the chip and preferably a single lead utilized as a ground connection. The power and ground leads are connected to an interdigitated lead array at the center of the chip carrier with the chip being secured to the chip carrier above the interdigitated pattern. The chip is bonded to a dielectric sliver which rests above a glass filler and bonding agent which fills the space between the interdigitated pattern and the sliver. The chip is hermetically sealed within the ceramic cap which is bonded to the chip carrier. Power and ground connections are made, from the chip directly to a pair of buses surrounding the interdigitated pattern rather than to leads extending outwardly to the edge of the chip carrier.

Abstract: A portion of the anode lead of a solid electrolyte capacitor is offset so that the remaining portion of the anode lead is coaxial with the anode riser, and these and the cathode lead are coplanar. The offset portion of the anode lead is bent transversely, and the riser is connected to this transverse. Preferably, the anode lead and the cathode lead are of different diameters.

Abstract: A large value capacitor having interdigitated electrodes embedded within a planar substrate of semiconductor material and a method for producing the capacitor are presented. Metallic material forming a plurality of individual electrodes is deposited within a plurality of isolated parallel spaced-apart planar recesses formed into the substrate from the planar surface by ion beam machining, etching, or the like. Alternate individual electrodes are electrically interconnected to form the interdigitated opposite electrodes of the capacitor with the dielectric comprising the high resistivity substrate material. Each of the interdigitated electrodes is connectable to other electronic members including members disposed on the same substrate.

Abstract: A process and a solid plane structure for minimizing delamination during sintering in the fabrication of multi-layer ceramic substrates, wherein the solid plane structure is designed to obtain maximum ceramic to ceramic interface contact.