Abstract: The invention relates to a method for producing an at least two-layered board. The board has a carrier layer, which consists at least partly of wood or lignocellulose-containing particles or fibers, and at least one coating, which consists of a WPC material and which is arranged on at least one face of the carrier layer. The method has the following steps: providing a finished carrier board (30) which forms the carrier layer; providing a WPC coating material, for example in the form of a granulate (32), on at least one of the two surfaces of the carrier board (30); and pressing the WPC coating material and the carrier board (30) under the influence of heat and pressure.

Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

Abstract: A method for manufacturing a device comprising an elastic member on a substrate includes steps of: forming a sacrificial layer by forming a plurality of sacrificial sub-layers on the substrate; forming a plate member in or on the sacrificial layers connected to the substrate and substantially parallel to a top surface of the substrate; and removing the sacrificial sub-layers after forming the plate member by removing the sacrificial sub-layers in an order different from the reverse order of forming the sacrificial sub-layers.

Abstract: A polishing slurry including an oxidant, a metal oxide dissolver, a metal inhibitor and water and having a pH from 2 to 5. The polishing slurry having a high metal-polishing rate, reducing etching rate and polishing friction, results in the production, with high productivity, of semiconductor devices reduced in dishing and erosion in metal wiring.

Abstract: In a nozzle hole image recognition method for picturing a nozzle hole of a liquid droplet ejection head which is filled with a function liquid and then performing image recognition thereof, the nozzle hole is pictured synchronously with application, to the liquid droplet ejection head, of a driving waveform which causes single-period micromotion of a meniscus surface of the nozzle hole. Thus, it is possible to provide: the nozzle hole image recognition method in which the image of the nozzle hole is recognized at a good accuracy in a state in which the liquid droplet ejection head is filled with the function liquid and a position correction method of a liquid droplet ejection head using it; a nozzle hole inspection method; a nozzle hole image recognition apparatus; and a liquid droplet ejection apparatus equipped therewith.

Abstract: A digital lithography system prints a large-area electronic device by dividing the overall device printing process into a series of discrete feature printing sub-processes, where each feature printing sub-process involves printing both a predetermined portion (feature) of the device in a designated substrate area, and an associated test pattern in a designated test area that is remote from the feature. At the end of each feature printing sub-process, the test pattern is analyzed, e.g., using a camera and associated imaging system, to verify that the test pattern has been successfully printed. A primary ejector is used until an unsuccessfully printed test pattern is detected, at which time a secondary (reserve) ejector replaces the primary ejector and reprints the feature associated with the defective test pattern. When multiple printheads are used in parallel, analysis of the test pattern is used to efficiently identify the location of a defective ejector.

Abstract: Pillars are formed in a fully integrated thermal inkjet printhead to prevent particles from entering into a nozzle chamber along an ink refill channel. The pillars are formed after a step of applying a thin film structure to a substrate. At one step, pits are etched through the thin film structure. At another step, material for an orifice layer is deposited into the pits. At another step, a firing chamber is etched into the orifice layer. At another step, a trench is etched into the backside of the wafer in the vicinity of the filled pits. The material filling each pit is not removed and remains in place to define the respective pillars. Two or more pillars are formed within the trench for each inkjet nozzle chamber. Alternatively pillars are formed by depositing material into the underside trench and performing photoimaging processes.

Abstract: There is provided a magnetic memory device which has a small switching current for a writing line and which has a small variation therein. A method for producing such a magnetic memory device includes: forming a magnetoresistive effect element; forming a first insulating film so as to cover the magnetoresistive effect element; forming a coating film so as to cover the first insulating film; exposing a top face of the magnetoresistive effect element; forming an upper writing line on the magnetoresistive effect element; exposing the first insulating film on a side portion of the magnetoresistive effect element by removing a part or all of the coating film; and forming a yoke structural member so as to cover at least a side portion of the upper writing line and so as to contact the exposed first insulating film on the side portion of the magnetoresistive effect element.

Abstract: The method for controlling the depth of polishing during a CMP process involves the deposition of a polishing stop layer at an appropriate point in the device fabrication process. The stop layer is comprised of a substance that is substantially more resistant to polishing with a particular polishing slurry that is utilized in the CMP process than a polishable material layer. Preferred stop layer materials of the present invention are tantalum and diamond-like carbon (DLC), and the polishable layer may consist of alumina. In one embodiment of the present invention the stop layer is deposited directly onto the top surface of components to be protected during the CMP process. A polishable layer is thereafter deposited upon the stop layer, and the CMP polishing step removes the polishable material layer down to the portions of the stop layer that are deposited upon the top surfaces of the components. The stop layer is thereafter removed from the top surface of the components.

Abstract: We have discovered a method of reducing the effect of material sputtered/etched during the preheating of a substrate. One embodiment of the method pertains to preheating a substrate which includes a metal-containing layer which is to be pattern etched subsequent to preheating. The method includes exposing the substrate to a preheating plasma which produces a deposit or residue during preheating which is more easily etched than said metal-containing layer during the subsequent plasma etching of said metal-containing layer.

Abstract: A method of batch fabrication of ultraminiature fiber optic pressure transducers including the steps of: providing a first substrate with a first sacrificial layer formed thereover; forming a plurality of light reflective diaphragm structures on the first sacrificial layer; forming a plurality of fiber stopper structures on the light reflective diaphragm structures; forming a plurality of fiber alignment cavity structures on the fiber stopper structures, the light reflective diaphragm structures, fiber stopper structures and fiber alignment cavity structures providing a plurality of fiber alignment assemblies; providing a second substrate with a second sacrificial layer formed thereover; forming a plurality of ferrule structures over the second sacrificial layer; inputting a plurality of fibers into the ferrule structures and sealing each of the ferrule structures to the fiber inserted therein, the ferrule structures and the fibers providing a plurality of fiber-ferrule assemblies; etching the second sacrific

Abstract: This patent a method of manufacturing a Dual Chamber Single Vertical Actuator Ink Jet Printer print head wherein an array of nozzles are formed on a substrate utilising planar monolithic deposition, lithographic and etching processes. Preferably, multiple ink jet heads are formed simultaneously on a single planar substrate such as a silicon wafer. The print heads can be formed utilising standard vlsi/ulsi processing and can include integrated drive electronics formed on the same substrate. The drive electronics preferably being of a CMOS type. In the final construction, ink can be ejected from the substrate substantially normal to the substrate.

Abstract: A method is provided for manufacturing a flat panel display in which a baseplate has a conductive row electrode deposited on it followed by an insulator. A conductive gate electrode is deposited over the insulator and a soft mask material is deposited over the conductive gate electrode. Microspheres are deposited on the soft mask material and an isotropic etch uses the microspheres as a mask to etch the soft mask material to form soft mask portions under the microspheres. The microspheres are removed and a hard mask material is deposited over the soft mask portions. The hard mask material is processed and chemical mechanical polished down to the soft mask portions which are removed by etching to leave a hard mask which is used by anisotropic etch process to form gate holes in the gate electrode. The gate holes are used to form emitter cavities into which emitters are deposited.

Abstract: A method of growing 4-H polytype silicon carbide crystals in a physical vapor transport system where the surface temperature of the crystal is maintained at less than about 2160.degree. C. and the pressure inside the PVT system is decreased to compensate for the lower growth temperature.