Patents Examined by Shane D Woolwine
  • Patent number: 10444994
    Abstract: Embodiments of the present disclosure relate to method and apparatus for scaling out storage devices, and scaled-out storage devices by establishing a cross-device link between a first storage device and a second storage device; exchanging configuration information of at least one of the first storage device and the second storage via the cross-device link; creating, in the first storage device, a shadow object corresponding to a real object in the second storage device; and creating, in the second storage device, a shadow object corresponding to a real object in the first storage device; wherein each shadow object can expose feature and/or state of a corresponding real object to users without implementing a functioning logic of the corresponding real object.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: October 15, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Jian Gao, Hongpo Gao, Geng Han, Xinlei Xu, Jibing Dong
  • Patent number: 10437732
    Abstract: In an embodiment, a processor includes at least one core and a first cache memory including a first plurality of sets having a first plurality of cache lines and associated metadata to store address information, recency information and a first indicator to indicate whether the cache line is associated with an oversubscribed set of a second cache memory. A first cache controller may be configured to base an eviction decision with regard to a first set of the first plurality of sets including a first cache line at least in part on the first indicator of the first cache line. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventor: Daniel Greenspan
  • Patent number: 10430717
    Abstract: A system for collecting elements as a basis for generating a social scenario useful to make a well-balanced good decision. A complex predicate template collecting apparatus includes: a simple predicate template DB storing simple predicate templates having positive or negative polarity values added; an object noun dictionary; a complex predicate template candidate extractor extracting complex predicate template candidates each formed of a combination of a word specified by the object noun dictionary and a simple predicate template, from a WEB archive; a sahen-noun polarity adder, a quantifier noun polarity adder and a trouble-noun polarity adder, determining polarity of a noun in each of the complex predicate template candidate; and a complex predicate template polarity calculator calculating polarity of a complex predicate template candidate by a combination of the polarity of the noun and the polarity of the simple predicate template included in the complex predicate template.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: October 1, 2019
    Assignee: National Institute of Information and Communications Technology
    Inventors: Chikara Hashimoto, Kentaro Torisawa, Motoki Sano, Yulan Yan, Yutaka Kidawara
  • Patent number: 10410120
    Abstract: A method for learning an object detector based on a region-based convolutional neural network (R-CNN) capable of converting modes according to aspect ratios or scales of objects is provided. The aspect ratio and the scale of the objects including traffic lights may be determined according to characteristics, such as distance from the object detector, shapes, and the like, of the object. The method includes steps of: a learning device instructing an RPN to generate ROI candidates; instructing pooling layers to output feature vector; and learn the FC layers and the convolutional layer through backpropagation. In this method, pooling processes may be performed depending on real ratios and real sizes of the objects by using distance information and object information obtained through a radar, a lidar or other sensors. Also, the method can be used for surveillance as humans at a specific location have similar sizes.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: September 10, 2019
    Assignee: Stradvision, Inc.
    Inventors: Kye-Hyeon Kim, Yongjoong Kim, Insu Kim, Hak-Kyoung Kim, Woonhyun Nam, SukHoon Boo, Myungchul Sung, Donghun Yeo, Wooju Ryu, Taewoong Jang, Kyungjoong Jeong, Hongmo Je, Hojin Cho
  • Patent number: 10402106
    Abstract: A storage module includes a set of memories. Each of the memories in the set of memories may be divided into a set of portions. A controller is configured to transfer data between the set of memories and a host connected through an interface. A set of channels connects the set of memories to the controller. The controller is also configured to select: a memory from the set of memories, a portion from the set of portions for the selected memory, and/or a channel from the set of channels, e.g., connected to the selected memory, based upon an identification (ID) associated with the data. The ID may be separate from the data and a write address of the data, and the selected memory, the selected portion, and the selected channel may be used to store the data.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: September 3, 2019
    Assignee: Memory Technologies LLC
    Inventor: Kimmo Juhani Mylly
  • Patent number: 10394707
    Abstract: In an example implementation according to aspects of the present disclosure, a memory controller is disclosed. The memory controller is communicatively coupleable to a memory resource having a plurality of memory resource regions, which may be associated with a plurality of computing resources. The memory controller may include a memory resource interface to communicatively couple the memory controller to the memory resource and a computing resource interface to communicatively couple the memory controller to the plurality of computing resources. The memory controller may further include a memory resource memory management unit to manage the memory resource.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: August 27, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Mitchel E. Wright, Michael R Krause, Melvin K. Benedict, Dwight L. Barron
  • Patent number: 10387315
    Abstract: A memory access profiling and region migration technique makes allocation and replacement decisions for periodic migration of most frequently accessed regions of main memory to least frequently accessed regions of a region migration cache, in background operations. The technique improves performance in sparsely-used memory systems by migrating regions of main memory corresponding to the working footprint of main memory to the region migration cache. A method includes profiling a stream of memory accesses to generate an access frequency ranked list of address ranges of main memory and corresponding access frequencies based on memory addresses in the stream of memory accesses. The method includes periodically migrating to a region migration cache contents of a region of main memory selected based on the access frequency ranked list. The method includes storing a memory address range corresponding to the contents of the region migration cache in a tag map.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: August 20, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Patrick N. Conway
  • Patent number: 10380026
    Abstract: A storage system implements a sparse, thinly provisioned logical-to-physical translation layer. The storage system may perform operations to modify logical-to-physical mappings, including creating, removing, and/or modifying any-to-any and/or many-to-one mappings between logical identifiers and stored data (logical manipulation operations). The storage system records persistent metadata to render the logical manipulation (LM) operations persistent and crash-safe. The storage system may provide access to LM functionality through a generalized LM interface. Clients may leverage the LM interface to efficiently implement higher-level functionality and/or offload LM operations to the storage system.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Swaminathan Sundararaman, Nisha Talagala, Robert Wipfel, Sriram Subramanian, Vladislav Bolkhovitin
  • Patent number: 10365845
    Abstract: Techniques for managing restriping of data across drives of a data storage system in a mapped-RAID environment. In response to addition of a drive to existing drives of the data storage system, all drive extents of the data storage system are mapped out in an effort to consume as much free space as possible across the drives. Having mapped out the drive extents, how many free extents remain on each drive is determined. If a quantity of free extents on a drive exceeds a predetermined threshold number, then that drive is logically marked as requiring restriping. Restriping of data is then performed for all logically marked drives. Once the restriping of the data is completed, a determination is made as to whether any further restriping of data across the drives of the data storage system is required, taking into account a relative wear and/or utilization of the respective physical drives.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: July 30, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Robert P. Foley, Peter Puhov, Ashok Tamilarasan
  • Patent number: 10360157
    Abstract: A memory system includes a memory device including a memory block, the memory block including a plurality of memory cell groups, an address translator that maps a logical address of a data to a physical address of the memory block, and a controller configured to divide the plurality of memory cell groups into a plurality of first memory cell groups and at least one second memory cell group, and control the address translator so that the address translator maps a logical address of a data to a physical address of the first memory cell groups of the memory block and not in the at least one second memory cell group and switches the at least one second memory cell group with a selected first memory cell group among the plurality of the first memory cell groups when a predetermined period of time elapses.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: July 23, 2019
    Assignee: SK hynix Inc.
    Inventors: Dong-Gun Kim, Yong-Ju Kim, Sang-Gu Jo, Do-Sun Hong
  • Patent number: 10353455
    Abstract: A three-dimensional stacked (3DS) memory module includes multiple memory chips physically integrated with a data I/O chip. The data I/O chip includes multiple data interfaces and multiple respectively corresponding data buffers. A memory controller routes data traffic through all available data interfaces for maximum bandwidth. In some circumstances, the memory controller directs the data I/O chip to de-activate one or more of the data interfaces (for example, to reduce power consumption). All subsequent data traffic to and from the memory module is routed through the remaining active interfaces. All physical addresses in the 3DS memory module are addressable through the remaining active interfaces. In some circumstances, the memory controller directs the data I/O chip to re-activate some or all of the de-activated data interfaces. Once re-activated, subsequent data traffic to and from the memory module can again be routed through all active interfaces.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kevin M. Mcilvain, Saravanan Sethuraman, Warren E. Maule, Kyu-hyoun Kim
  • Patent number: 10331355
    Abstract: A control device, including: a first processor; a second processor which has a higher performance than the first processor; and a storage in which data is stored so as to be readable and writable by the second processor, wherein a part of the storage is usable as a common storage area which is readable and writable by the first processor and the second processor, in reading operation, the second processor reads first data from out of the common storage area in the storage and writes the first data to the common storage area, and the first processor reads the first data from the common storage area, and in writing operation, the first processor writes second data to the common storage area, and the second processor stores the second data out of the common storage area in the storage.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 25, 2019
    Assignee: CASIO COMPUTER CO., LTD.
    Inventors: Naoto Toda, Tatsuya Sekitsuka
  • Patent number: 10324847
    Abstract: A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with a first memory address in a cache memory system that supports synonyms, wherein the second memory address and the first memory address each comprise a synonym identifier. The method also includes determining a set of differing bits within the synonym identifier of the first memory address and the second memory address, and including the set of differing bits within a set of synonym generation bits for the cache memory system. A corresponding apparatus, computer program product, and system are also disclosed herein.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Martin Recktenwald, Willm Hinrichs
  • Patent number: 10324846
    Abstract: A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with a first memory address in a cache memory system that supports synonyms, wherein the second memory address and the first memory address each comprise a synonym identifier. The method also includes determining a set of differing bits within the synonym identifier of the first memory address and the second memory address, and including the set of differing bits within a set of synonym generation bits for the cache memory system. A corresponding apparatus, computer program product, and system are also disclosed herein.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Martin Recktenwald, Willm Hinrichs
  • Patent number: 10318423
    Abstract: A request is received to access physical information of a memory unit included in a memory device. A determination is made whether the physical information is available in a physical information table present in a memory cache. If the physical information of the memory unit is available in the table, the physical information is accessed from the table. If the physical information is not available in the table, a global directory in the memory cache is accessed, which indicates locations in a non-volatile memory that store the total number of the physical information blocks. From the global directory, a particular location in the non-volatile memory storing a particular physical information block that includes the physical information of the memory unit is determined. The particular physical information block is loaded into the table and the physical information of the memory unit is accessed from the particular physical information block.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 11, 2019
    Assignee: Macronix International Co., Ltd.
    Inventor: Yi-Chun Liu
  • Patent number: 10310769
    Abstract: A memory system may include a memory device comprising a plurality of memory blocks each having a plurality of pages; and a controller suitable for storing data in a first memory block among the memory blocks, storing map data of the data in a second memory block among the memory blocks, and scanning the map data by performing filtering on logical information of the data in response to a command.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: June 4, 2019
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 10296245
    Abstract: A method of rebuild operation of a memory controller, the method includes: searching a reference page information stored in a first memory block when a power is restored after occurrence of a sudden power off; identifying a reference page of a second memory block and storing the reference page information of the reference page into the first memory block when the reference page information is determined not to be stored in the first memory block; and performing a rebuild operation to data stored in the second memory block based on the reference page information stored in the first memory block.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 21, 2019
    Assignee: SK hynix Inc.
    Inventor: JangHwan Jun
  • Patent number: 10289722
    Abstract: A multi-level cache system may include a server with a processor and memory. The memory may include a database cache system for use with a distributed database system. The server may also include a Solid State Drive that may include a key-value store and a second storage device that may store a backend database. The key-value store may act as a second level cache to the database cache system.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: May 14, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Inseok Stephen Choi, Byoung Young Ahn, Yang Seok Ki
  • Patent number: 10289339
    Abstract: A DIMM includes a DRAM device and a non-volatile memory device. The DIMM is configured to determine that first data stored on the DRAM device is modified data and that second data stored on the DRAM device is unmodified data, and perform a save data operation to transfer the data from the DRAM device to the non-volatile memory device, wherein the save data operation comprises transferring the first data and not transferring the second data.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Dell Products, LP
    Inventors: Vadhiraj Sankaranarayanan, John E. Jenne, Quy N. Hoang
  • Patent number: 10275168
    Abstract: A method and technique are provided for providing a service address space. The method includes providing a service co-processor with a service address space attached to a main processor. The main processor is provided with a main address space. Instructions that modify the main address space are intercepted, storage delta packets are generated based on intercepted instructions, and the storage delta packets are sent to a service co-processor maintaining a service address space.
    Type: Grant
    Filed: July 15, 2018
    Date of Patent: April 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David J. Harman, Neil W. Leedham, Kim P. Walsh, Andrew Wright