Abstract: A method of rebuild operation of a memory controller, the method includes: searching a reference page information stored in a first memory block when a power is restored after occurrence of a sudden power off; identifying a reference page of a second memory block and storing the reference page information of the reference page into the first memory block when the reference page information is determined not to be stored in the first memory block; and performing a rebuild operation to data stored in the second memory block based on the reference page information stored in the first memory block.

Abstract: A DIMM includes a DRAM device and a non-volatile memory device. The DIMM is configured to determine that first data stored on the DRAM device is modified data and that second data stored on the DRAM device is unmodified data, and perform a save data operation to transfer the data from the DRAM device to the non-volatile memory device, wherein the save data operation comprises transferring the first data and not transferring the second data.

Abstract: A multi-level cache system may include a server with a processor and memory. The memory may include a database cache system for use with a distributed database system. The server may also include a Solid State Drive that may include a key-value store and a second storage device that may store a backend database. The key-value store may act as a second level cache to the database cache system.

Abstract: A method and technique are provided for providing a service address space. The method includes providing a service co-processor with a service address space attached to a main processor. The main processor is provided with a main address space. Instructions that modify the main address space are intercepted, storage delta packets are generated based on intercepted instructions, and the storage delta packets are sent to a service co-processor maintaining a service address space.

Abstract: In a multi-level cache system, a logic may be responsible for calculating the appropriate sizes for a database cache and a key-value store. Reception circuitry may receive a hit rate for the database cache, a reuse distance for the key-value store, and a user-selected quality of server. An adaption calculator may then calculate a target size for the database cache and a target size for the key-value store. Transmission circuitry may then transmit the target size for the database cache and the target size for the key-value store for use in the multi-level cache system.

Abstract: A system and technique are provided for providing a service address space. The system includes a service co-processor provided with a service address space. The service co-processor is attached to a main processor where the main processor is provided with a main address space. The service co-processor creates and maintains an independent copy of the main address space in the form of the service address space. The service co-processor updates the service address space with storage delta packets received from the main processor, and the service co-processor performs diagnostic services based on command packets received from the main processor.

Abstract: According to one embodiment, a memory system includes a first memory including a message queue having first to nth addresses (n?2, n is natural number), a first pointer showing one of the first to nth addresses, and a second pointer showing one of the first to nth addresses, a monitor unit which detects whether the first and second pointers show the first address, and a processing unit which changes an address shown by the first pointer from the first address to an ith address (n?i?2, i is natural number) when the first and second pointers show the first address. An address shown by the second pointer is incremented from the first address to a (j+1)th address (j?1, j is natural number) when first to jth messages are queued in the first to jth addresses.

Abstract: In accordance with embodiments of the present disclosure, a method of transmitting data in an information handling system may include receiving, at a hardware logic device from a plurality of memory storage devices communicatively coupled to the hardware logic device, a plurality of command fetch requests; analyzing metadata associated with each of the plurality of command fetch requests in order to serialize the plurality of command fetch requests in a chronological order; and communicating the coalesced command fetch requests in the chronological order to a memory having stored thereon commands responsive to the coalesced command fetch requests.

Abstract: Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.

Abstract: Scalable architectures provide resiliency and redundancy and are suitable for cloud deployment. The architectures support extreme data throughput requirements. In one implementation, the architectures provide a serving layer and an extremely high speed processing lane. With these and other features, the architectures support complex analytics, visualization, rule engines, and centralized pipeline configuration.

Abstract: A memory allocation system is provided and includes nodes, one or more memories, and an allocation interface. Each of the nodes includes a respective set of processors. The one or more memories include memory elements for storing threads. The memory elements refer to respective portions of the one or more memories and are accessible to at least one of the nodes. The allocation interface is configured to allocate the memory elements to lockless list structures. Each of the lockless list structures is allocated to a respective set of the memory elements. The lockless list structures are partitioned for the processors. The allocation interface is configured to receive requests from the processors for the memory elements and adjust allocation of the memory elements between the lockless list structures according to a balancing metric.

Abstract: A method of performing memory synchronization operations is provided that includes receiving, at a programmable cache controller in communication with one or more caches, an instruction in a first language to perform a memory synchronization operation of synchronizing a plurality of instruction sequences executing on a processor, mapping the received instruction in the first language to one or more selected cache operations in a second language executable by the cache controller and executing the one or more cache operations to perform the memory synchronization operation. The method further comprises receiving a second mapping that provides mapping instructions to map the received instruction to one or more other cache operations, mapping the received instruction to one or more other cache operations and executing the one or more other cache operations to perform the memory synchronization operation.

Abstract: Techniques are described for managing lifecycles of offline data on mobile devices. In some implementations, offline data instances stored at a mobile device are monitored based on a set of memory management rules. A memory management process maintains an offline data instance table identifying each of the set of monitored offline data instances stored at the mobile device and associates each instance with a timestamp identifying a most recent time of access satisfying at least one access type as defined in the set of memory management rules. In response to determining that a trigger associated with performing a memory management process has occurred, a period of time parameter from a last access corresponding to deletion is identified. The parameter is compared to a current time and the most recent time of access for each instance, and instances where the comparison meets or exceeds the period of time parameter are deleted.

Abstract: A system and method for managing data in a storage system are provided. A system and method may include receiving a data block and a logical address and identifying, in a set of address sequence range (ASR) objects, an ASR object having an address sequence range that is close to the logical address. A system and method may include storing the data block in the storage system, and updating the ASR object to include the logical address.

Abstract: The disclosed computer-implemented method for load balancing backup data may include (1) receiving a request to backup files in a multi-node computing cluster, (2) identifying a backup distribution of the files among multiple backup clients, (3) reading an initial data block of a current file from a data node in the cluster, (4) reading a copy of the initial data block of an additional file from another data node in the cluster, (5) reading a subsequent data block of the current file from the data node in the cluster, and (6) balancing backup of the current and additional files among the data node and the another data node by reading a copy of a subsequent backup data block of the additional file from the another data node in the multi-node computing cluster. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method, computer program product, and/or system for performing a selection of a plurality of auxiliary storage sites in a multi-target environment in preparation for a hyper exchange are/is provided. To perform the selection, a failure is first detected with respect to a primary storage site in the multi-target environment. Then, aggregate weights are determined based on a management policy for the plurality of auxiliary storage sites. In turn, an auxiliary storage site with a first aggregate weight is selected from the plurality of auxiliary storage sites. With the auxiliary storage site selected, the hyper exchange of a plurality of systems in a multi-target environment in response to the failure is triggered from the primary storage site to the auxiliary storage site with the first aggregate weight.

Abstract: A memory system may include a memory device including a plurality of memory blocks each having a plurality of pages suitable for storing data requested from a host, and a controller including a memory, and suitable for storing write data corresponding to a write command received from the host in a first memory block of the memory blocks, storing first and second map data corresponding to the write data written to the first memory block in a second memory block of the memory blocks, and storing a segment list for first segments of the first map data in the memory.

Abstract: A memory system may include a memory device comprising a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of pages having a plurality of memory cells coupled to a plurality of word lines, the memory device being suitable for storing read data and write data requested by a host in the plurality of pages, and a controller suitable for grouping the plurality of pages included in the memory blocks, dividing each of the memory blocks into a plurality of sub-memory blocks, programming data corresponding to a write command, performing an update program on the data programmed into the first memory block into the memory blocks in response to a write command, and storing a map list for the sub-memory blocks included in the first memory block in accordance with the update program.