Abstract: A branch predictor outputs either a predicted conditional branch or an inverted predicted conditional branch as a final branch prediction outcome, in response to a predicted accuracy history signal based on one or more accuracy history bits. According to the accuracy history bit, it is determined whether the branch prediction outcome of the branch predictor is correct. If the predicted conditional branch is correct, the branch predictor outputs the predicted conditional branch, and if the predicted conditional branch is not correct, the branch predictor outputs the inverted predicted conditional branch, in response to the predicted accuracy history signal. For performing this process, the branch prediction appends an accuracy history table and a multiplexer to a conventional branch predictor, so that the branch prediction according to the present invention can reduce the misprediction with relatively simple circuitry and low hardware cost.

Abstract: An apparatus for storing predicted return addresses of instructions being executed by a pipelined processor, the apparatus includes a two part return address buffer that includes a speculative return address buffer and a committed return address buffer, both of which having multiple entries that may include predicted return addresses that have been pushed onto the return buffer.

Abstract: A processor supports multiple operand sizes (e.g. 8, 16, 32, and 64 bit operand sizes, in one embodiment). Additionally, the processor determines how to update a destination register when an operand size less than the largest operand size is used. In one embodiment, the processor determines whether or not to zero extend the result responsive to the operand size used. In one particular embodiment, the processor zero extends 32 bit operands and does not zero extend 8 or 16 bit operands. Furthermore, the processor may preserve the value in at least part of the remaining portion of the register when 8 or 16 bit operand sizes are used.

Abstract: A programmable processor includes a execution pipeline and an exception pipeline. The execution pipeline may be a multi-stage execution pipeline that processes instructions. The exception pipeline may be a multi-stage exception pipeline that propagates exceptions resulting from the execution of the instructions. The execution and exception pipelines may have the same number of stages and may operate on the same clock cycles. When an instruction passes from a stage of the execution pipeline to a later stage of the execution pipeline, an exception may similarly pass from a corresponding stage of the exception pipeline to a corresponding later stage of the exception pipeline.

Abstract: A processor supports a mode in which the default operand size is 32 bits, but which supports operand size overrides to 64 bits. Furthermore, the default operand size may automatically be overridden to 64 bits for instructions having an implicit stack pointer reference and for near branch instructions. The overriding of the default operand size may occur without requiring an operand size override encoding in these instructions. In one embodiment, the instruction set specifying the instructions may be a variable byte length instruction set (e.g. x86), and the operand size override encoding may be a prefix byte which increases the instruction length.