Abstract: A method and computer program product for garbage collection sensitive load balancing is disclosed for memory tuning for garbage collection and CPU utilization optimization An application is benchmarked across multiple different heap sizes to accumulate garbage collection metrics and the garbage collection metrics accumulated during benchmarking are utilized to compute both CPU utilization and garbage collection time for each of a selection of candidate heap sizes. One of the candidate heap sizes can be matched to a desired CPU utilization and garbage collection time, and the matched one of the candidate heap sizes can be applied to a host environment.

Abstract: A system and method provides active inheritance on memory writes such that entities issuing later writes ensure that the effects of earlier writes to the same memory block will be seen. A write chain is preferably formed by storing information and state in miss address file (MAF) entries maintained by the entities. The write chain links the entities requesting write access to the memory block. When the desired memory block becomes available, the information and state stored at the MAF entries is then utilized by each entity in ensuring that all earlier writes are complete before its write is allowed to complete.

Abstract: In a disk control device arranged to include a CPU, a plurality of channel control units, a plurality of disk control units, a cache memory, and a data transfer integrated circuit communicably connected to the cache memory via a plurality of data buses, when receiving a request for access to the cache memory from any one of the CPU, the channel control units and the disk control units, the data transfer integrated circuit provides access to the cache memory by use of a certain number of one or ones of the data buses, which number is determinable in accordance with a transfer data length that is set in the access request.

Abstract: Apparatus and methods for synchronizing a distributed mirror. A computer system incorporating the invention may divide a mirror source into N chunks, assigning N storage processors responsibility for respective chunks of the mirror. The storage processors then may communicate among themselves to synchronize a distributed mirror. The storage processors may communicate mirror source blocks or their addresses and host-initiated (user) data requests. A storage processor may assist the synchronization of a mirror. The processor may accept responsibility for a chunk of a mirror source and communicate with a second storage processor responsible for another chunk of the mirror source to synchronize the mirror. The storage processor may track addresses of source blocks currently in use for synchronization, as well as addresses of source blocks to be synchronized after the blocks currently in use for synchronization.

Abstract: Method and apparatus using a Content Addressable Memory for sorting a plurality of data items is presented. The data items to be sorted are stored in the Content Addressable Memory. A plurality of bit-by-bit burst searches are performed on the contents of the Content Addressable Memory with all other bits in the search key masked. The number of burst searches is proportional to the total number of bits in the data items to be sorted. The search is deterministic dependent on the number of bits in each data item on which a sort is performed and on the number of data items to be sorted.

Abstract: A method of passing a location of a data interface. The method involves storing a first pointer in an architected location for locating information related to a system firmware read only memory (ROM). A portion of memory is allocated for a data structure that is an interface for handing off system component information. A second pointer is stored in a memory location pointed to by the first pointer. The second pointer points to the data structure.

Abstract: A disk drive is disclosed which pre-computes first seek parameters to seek to a continuation track storing read-ahead data, and second seek parameters to seek to a target track of a next command. An abort window is also computed for aborting a read-ahead operation early in order to seek to the target track of the next command. If the head enters the abort window, the disk drive is programmed with the second seek parameters to seek to the target track of the next command. If the read-ahead operation requires a seek to the continuation track prior to the head entering the abort window, the disk drive is programmed with the first seek parameters to seek to the continuation track.

Abstract: A computer system may include a host computer system and a storage device such as a tape device that includes one or more tape drives. The host computer system may be configured to provide commands to the storage device and to initiate a timeout period for each command provided to the storage device. The host computer system may be configured to initiate a first timeout period if a first type of command is provided to the storage device, to initiate a second timeout period if a second type of command is provided to the storage device, and to initiate a third timeout period if a third type of command is provided to the storage device, where the first timeout period, the second timeout period, and the third timeout period each have a different duration.

Abstract: The processors #0 to #3 execute a plurality of threads whose execution sequence is defined, in parallel. When the processor #1 that executes a thread updates the self-cache memory #1, if the data of the same address exists in the cache memory #2 of the processor #2 that executes a child thread, it updates the cache memory #2 simultaneously, but even if it exists in the cache memory #0 of the processor #0 that executes a parent thread, it doesn't rewrite the cache memory #0 but only records that rewriting has been performed in the cache memory #1. When the processor #0 completes a thread, a cache line with the effect that the data has been rewritten recorded from a child thread may be invalid and a cache line without such record is judged to be effective. Whether a cache line which may be invalid is really invalid or effective is examined during execution of the next thread.

Abstract: A memory subsystem and a method for use in accessing a memory system are disclosed. The memory subsystem comprising a plurality of SDRAM memory modules and a memory controller. The memory controller is capable of waiting to generate a memory clock signal for each of the SDRAM memory modules until a valid window for a control signal and an address signal; generating the memory clock signals during the valid window, and generating the control and address signals. The method comprises: waiting for a valid window for a control signal and an address signal; generating a memory clock during the valid window; and generating the control signal and the command signal a predetermined period of time after generating the memory clock signal.

Abstract: A method is provided for manipulating a compressed translation table in a memory expansion technology system. The method comprises swapping contents of an output buffer with contents of a compression buffer, disabling compression for compression translation table entries corresponding to the content swapped to the compression buffer, and packaging entries of a compression translation table corresponding to the contents swapped to the compression buffer, wherein packaged compression translation table entries are accessible to a computer system for addressing the contents swapped to the compression buffer.

Abstract: A translation lookaside buffer mechanism is described incorporating a set associative translation lookaside buffer operating in parallel with a fully associative translation lookaside buffer. Lockdown entries are stored within the fully associative translation lookaside buffer and non-lockdown entries are stored within the set associative translation lookaside buffer. Victim selection for the fully associative translation lookaside buffer 18 is performed using a control register within a coprocessor which is set under operating system software control.

Abstract: The present invention is a method and system for upgrading drive firmware on a drive within a distributed data storage system in a manner that is transparent and non-disruptive to the host system operations. The method and system allow for normal read and write operations to occur during the firmware upgrade process, even while the primary disk drive is off-line, through alteration of the controller read and write policies. A mapping file is created on a temporary storage device to reduce the necessary time period of the upgrade process. This time period is further reduced in a mirrored storage system or in a system having a spare drive, where a logging file is created to store the data diverted from the primary disk drive during the upgrade process. An advantage is the ability to maintain storage system redundancy during the upgrade process.

Abstract: A secure flash memory device includes a connection port, a microcontroller, a flash memory, and a security program. The security program provides pass code security between a computer connected to the connection port and the flash memory. The microcontroller controls the flow of data between the computer and the flash memory as allowed by the security program. The security program is stored in the flash memory or in the microcontroller and can be executed by the computer, when the microcontroller receives flash memory access requests from the connection port.

Abstract: The present invention provides a flash memory management system and method with increased performance. The flash memory management system provides the ability to efficiently manage and allocate flash memory use in a way that improves reliability and longevity, while maintaining good performance levels. The flash memory management system includes a free block mechanism, a disk maintenance mechanism, and a bad block detection mechanism. The free block mechanism provides efficient sorting of free blocks to facilitate selecting low use blocks for writing. The disk maintenance mechanism provides for the ability to efficiently clean flash memory blocks during processor idle times. The bad block detection mechanism provides the ability to better detect when a block of flash memory is likely to go bad. The flash status mechanism stores information in fast access memory that describes the content and status of the data in the flash disk.

Abstract: In a storage area network having a host device and a consolidated storage array (CSA), one of the storage arrays of the CSA acts as a primary device of the CSA to form logical data volumes across one or more of the total storage arrays of the CSA. The logical data volumes typically have performance requirements that cannot be met by a single storage array. Upon receipt of a command from the host device to create one of the logical data volumes, the CSA primary device analyzes the storage arrays to determine a combination thereof, across which the logical data volume will be striped, that best satisfies the performance requirements. The CSA primary device configures these storage arrays to form the logical data volume and sends striping information, which defines the logical data volume, to the host device. Striping software based on the host device responds to the striping information to access the logical data volume.

Abstract: A nonvolatile memory device is operable in a serial mode and in a parallel mode. The architecture of the nonvolatile memory device is based upon the structure already present in a standard memory, but includes certain modifications. These modifications include the addition of a timing state machine for the various memory access phases (i.e., writing and reading data), and the addition of an internal bus and related logic circuits for disabling the internal address bus of the standard memory when the nonvolatile memory device operates in the serial mode.

Abstract: A system and method are presented for indicating active tag bits within valid entries of a dual-clock FIFO data buffer, used to transfer data between two clock domains. Data (containing tag bits) are written to the FIFO and read from the FIFO using separate clocks. Data writes are synchronous with the first clock, while reads are synchronous with the second clock. A FIFO entry is “valid” after data has been written to it, and before it is read. The system disclosed herein identifies the valid FIFO entries and generates a set of logic outputs, synchronized to the second clock (i.e., the read clock). Each output corresponds to one of the tag bit positions, and is HIGH if the corresponding tag bit is HIGH in any of the valid entries. This creates a means of detecting active tag bits in the FIFO without having to actually read each entry. Since the tag bits convey important information about the source and nature of the data, this detection system may expedite the data transfer.

Abstract: A data storage and retrieval system which includes one or more hard disks individually housed in a portable hard disk drive unit, a first information transfer station capable of communicating with one or more first servers, and a second information transfer station capable of communicating with one or more second servers. A method to transfer information between those first servers, second servers, and hard disks. A data storage and retrieval system comprising computer useable medium having computer readable program code disposed therein, where that computer readable program code comprises a series of computer readable program steps to implement Applicants' method.

Abstract: A clocking system and method in a point-to-point bus configuration overcomes the limitations of conventional approaches. In one embodiment, the present invention ensures the same phase relationship for the write clock in the write direction for all data transfers between modules, and similarly the same phase relationship for the read clock in the read direction for all data transfers between modules, regardless of module location. In another embodiment, on a given module, all transfers of data between a data buffer and a memory device in both read and write directions are clocked by a read clock signal and a write clock signal that have the same phase relationship and have the same propagation delay as the data bus between the buffer and the memory device.