Abstract: A run-length decoder arranged to produce output signals in groups, each group being output in parallel. The decoder includes a position register which indicates the position, within a group, of the latest transition between signal values. The contents of this register are added to the incoming run-length code so as to calculate the number of groups to be output before the next transition and the position within the group of that next transition. The calculated number of groups is then output and a transition is introduced into the calculated position in the next group to be output.

Abstract: A 16-bit D/A converter formed on a single monolithic IC chip and having two cascaded stages each including a 256-R resistor-string DAC. The first stage employs a switch selector system capable of selecting any two adjacent taps of the resistor string to produce a segment voltage to be applied across the second stage resistor string. The resistor strings are formed as elongate thin film strips configured as a single, unbent body having integral voltage tap nipples evenly-spaced along both sides of the strip. Buffer amplifiers between the cascaded stages incorporate NMOS and PMOS-cascoded bipolar current sources in a non-epitaxial structure on a P-type substrate.