Abstract: A partially blocking data cache having improved microprocessor performance while maintaining data consistency between external memory and cache memory. The data cache of the present invention is used in a computer system and is partially blocking in that this cache will block the execution of any store instructions subsequent to an outstanding load instruction that missed the cache. The present invention offers increased microprocessor efficiency by allowing execution of subsequent load instructions while less than a predetermined number of preceding load instructions are still outstanding. The present invention utilizes a counter within the data cache unit to track the number of outstanding load misses. The present invention provides increased performance without undue or overly complex modifications to existing caching systems.

Abstract: A computer system predicts an address required to execute a current iteration of a program instruction based on addresses required to execute previous iterations of the same program instruction. The system stores an address required to execute the previous iteration of the program instruction, and determines differences between addresses required to execute successive iterations of the program instruction prior to the current iteration. The system also determines and stores a current value of a delta, and predicts the address required to execute the current iteration of the program instruction based on the address required to execute the previous iteration of the program instruction plus the current value of the delta.

Abstract: A multi-bit SP-Vector is created to record the history of each page of a process. Each time an ager scans the accessed/not accessed bit flag of the page tables entires, the SP-Vector is updated to reflect whether or not the corresponding page was accessed. A table is created to provide ready update and interpretation information for each SP-Vector depending upon whether or not the last scan indicated an accessed or not accessed status. The table further contains a running total of the number of accesses for each SP-Vector which allows a rapid determination of which pages have been accessed the least. The least accessed pages may then be selected for swapping out of physical memory.

Abstract: A fault-tolerant high performance mirrored disk subsystem is described which has an improved disk writing scheme that provides high throughput for random disk writes and at the same time guarantees high performance for disk reads. The subsystem also has an improved recovery mechanism which provides fast recovery in the event that one of the mirrored disks fails and during such recovery provides the same performance as during non-recovery periods.Data blocks or pages which are to be written to disk are temporarily accumulated and sorted (or scheduled) into an order (or schedule) which can be written to disk efficiently, which in a preferred embodiment is in accordance with the physical location on disk at which each such block will be written. This also generally corresponds to an order which is encountered by a writ head during a physical scan of a disk. The disks of a mirrored pair are operated out of phase with each other, so that one will be in read mode while the other is in write mode.

Abstract: A method and system for minimizing seek affinity and enhancing write sensitivity in a direct access storage device (DASD) array are disclosed. SEEK affinity and WRITE efficiency are preserved in which logical cylinders, as recorded on the DASD array, are managed as individual log structured files (LSF). Tracks or segments of data and parity blocks having the same or different parity group affinity and stored on the same or different DASD cylindrical addresses are written into a directory managed buffer. Blocks having the same parity affinity and written to counterpart cylinders are written out from the buffer to spare space reserved as part of each DASD cylinder. Otherwise, blocks are updated in place in their DASD array location.

Abstract: The present invention is a method and apparatus for efficiently using existing cache memory in a virtual memory computer system for servicing different demands for such memory. Moreover, the method and apparatus of the present invention, provides a way for authenticating untrusted virtual memory managers (VMMs) and untrusted pagers, which use and supply such caching services. The method and apparatus for authenticating the VMM and pagers can be practiced in an object oriented programming environment or in a non-object oriented environment.

Abstract: A Single Inline Memory Module (SIMM) support system enables a computer system to recognize and address 1-Mbyte, 4-Mbyte and 16-Mbyte SIMMs installed in a receiving socket having only a number of pins sufficient to address the 1-Mbyte and 4-Mbyte SIMMs. The capacity of the SIMM is determined by a TYPE signal on a predetermined pin of the installed SIMM which is connected to a pull-up resistor of the SIMM support circuitry and generates a TYPE signal. If the TYPE signal is a logic low, the installed SIMM has a 1-Mbyte capacity. If the TYPE signal is a logic high, the installed SIMM has a 4-Mbyte or a 16-Mbyte capacity. In order to remain pin compatible with 1-Mbyte and 4-Mbyte SIMMs, a 16-Mbyte SIMM cannot have any additional pins to address the additional memory locations. Thus, the TYPE signal shares a pin with the most significant address bit required to address the 16-Mbyte SIMM.