Abstract: A refresh control system and method for refreshing DRAM memory in a data processing system, such as a communications system, are disclosed. A timer increments a refresh request counter each time that a desired refresh interval elapses. The contents of the refresh request counter is compared with the contents of a burst refresh counter, and a bus request signal generated responsive to the contents differing from one another, such difference indicating that a refresh operation should be performed. The bus arbitration scheme assigns no higher priority to the refresh priority request than for other bus operations; at such time as bus access is granted to the refresh operation, burst refresh is performed until the contents of the burst refresh counter again match the refresh request counter, at which time the bus is released.